Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures

Coarse-grain reconfigurable architectures have been a matter of intense research in the last few years. They promise to be more adequate for computational tasks due to their better efficiency and bigger speed. As the coarse granularity implies also a reduction of fiexibility, a universal architecture seems to be hardiy feasible. Based on the KressArray architecture family, a design-space exploration system is being impiemented, which supports the designer in finding an appropriate architecture for a given application domain. By analysing the results of a number of different experimental mappings, the system derives suggestions how the architecture can be enhanced. This paper presents an analyser tool, which allows the generation of such suggestions using approximate reasoning based on fuzzy logic. The tool is flexible enough to support different data gathering methods and an extensible rule set.

[1]  Seth Copen Goldstein,et al.  PipeRench: a co/processor for streaming multimedia acceleration , 1999, ISCA.

[2]  Reiner W. Hartenstein,et al.  A datapath synthesis system for the reconfigurable datapath architecture , 1995, ASP-DAC '95.

[3]  Vivek Sarkar,et al.  Baring It All to Software: Raw Machines , 1997, Computer.

[4]  J.M. Rabaey.  Low-power silicon architectures for wireless communications , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[5]  André DeHon,et al.  MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[6]  D. Bhatia,et al.  Reconfigurable computing , 1997, Proceedings Tenth International Conference on VLSI Design.

[7]  Donald Yeung,et al.  Exploring optimal cost-performance designs for Raw microprocessors , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[8]  Miodrag Potkonjak,et al.  System-level design guidance using algorithm properties , 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.

[9]  Peter M. Athanas,et al.  Colt: an experiment in wormhole run-time reconfiguration , 1996, Other Conferences.

[10]  B. R. Gainfs.  Foundations of fuzzy reasoning , 1976 .

[11]  Asia.  Proceedings of the ASP-DAC'95/CHDL'95/VLSI'95 : Asia and South Pacific Design Automation Conference, IFIP International Conference on Computer Hardware Description Languages and Their Applictions, IFIP International Conference on Very Large Scale Integration, August 29-September 1, 1995, Makuhari Me , 1995 .

[12]  Reiner W. Hartenstein,et al.  Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract) , 2000, FPGA '00.

[13]  Reiner W. Hartenstein.  The microprocessor is no longer general purpose: why future reconfigurable platforms will win , 1997, 1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon.

[14]  Miodrag Potkonjak,et al.  A methodology for guided behavioral-level optimization , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[15]  Reiner W. Hartenstein,et al.  Synthesis and Domain-Specific Optimization of KressArray-Based Reconfigurable Computing Engines , 2000 .

[16]  Carl Ebeling,et al.  RaPiD - Reconfigurable Pipelined Datapath , 1996, FPL.

[17]  Brian R. Gaines,et al.  Systems Theory in the Social Sciences (ISR20), H. Bossel, S. Klaczko, N. Müller (Eds.). Birkhäuser Verlag, Basel (1976), 552, SF 48. ISBN 3-7643-0822-2 , 1976 .

[18]  Reiner W. Hartenstein,et al.  Mapping Applications onto Reconfigurable Kress Arrays , 1999, FPL.

[19]  Jean Vuillemin,et al.  A reconfigurable arithmetic array for multimedia applications , 1999, FPGA '99.