AVERSATILEARCHlTECIWREFORVISI IMPLEMENTATION OF THE VITEZtBIALGO€U'I'HM

We study the implementation of the Viterbi algorithm, focusing on the problem of the addcompare-select (ACS) operation, which is a severe bottleneck for high speed VLSI implementation. We propose a new architecture based on a de Bruijn network, which is adjustable to various performance levels (with full or limited parallelism) and exhibits good area-time performances. A practical layout for VLSI implementation is also discussed.