A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL

Abstract—We describe a digitally controlled oscillator (DCO) which compensates the frequency variations for process, voltage, and temperature (PVT) variations with an accuracy of ±2.6% at 2.5 GHz. The DCO includes an 8 phase current-controlled ring oscillator, a digitally controlled current source (DCCS), a process and temperature (PT)-counteracting voltage regulator, and a bias current generator. The DCO operates at a center frequency of 2.5 GHz with a wide tuning range of 2.2 GHz to 3.0 GHz. At 2.8 GHz, the DCO achieves a phase noise of -112 dBc/Hz at 10 MHz offset. When it is implemented in an all-digital phase-locked loop (ADPLL), the ADPLL exhibits an RMS jitter of 8.9 ps and a peak to peak jitter of 77.5 ps. The proposed DCO and ADPLL are fabricated in 65 nm CMOS technology with supply voltages of 2.5 V and 1.0 V, respectively. Index Terms—Digitally controlled oscillator, ring oscillator, PVT compensated DCO, PT-counteracting voltage regulator, all-digital phase-locked loop

[1]  I. Filanovsky,et al.  Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits , 2001 .

[2]  Soon-Jyh Chang,et al.  On-chip reference oscillators with process, supply voltage and temperature compensation , 2010, 2010 International Symposium on Next Generation Electronics.

[3]  Suhwan Kim,et al.  A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  Xuan Zhang,et al.  A Low-Power, Process-and- Temperature- Compensated Ring Oscillator With Addition-Based Current Source , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Yvon Savaria,et al.  Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI , 1999 .

[6]  Kadaba Lakshmikumar,et al.  A Process and Temperature Compensated Two-Stage Ring Oscillator , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[7]  Deok-Soo Kim,et al.  A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller , 2010, IEEE Journal of Solid-State Circuits.

[8]  Mohammad Rafiqul Haider,et al.  A wideband Injection Locked Frequency Divider based on a process and temperature compensated ring oscillator , 2008, 2008 IEEE Radio and Wireless Symposium.

[9]  Suhwan Kim,et al.  A 1.0–4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control , 2011, IEEE Journal of Solid-State Circuits.

[10]  P. Nilsson,et al.  A digitally controlled PLL for SoC applications , 2004, IEEE Journal of Solid-State Circuits.

[11]  Do-Un Jeong,et al.  Phase-frequency detecting time-to-digital converter , 2009 .

[12]  Woo-Young Choi,et al.  On-Chip Compensation of Ring VCO Oscillation Frequency Changes Due to Supply Noise and Process Variation , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.