Cryogenic Characterization of 28-nm FD-SOI Ring Oscillators With Energy Efficiency Optimization

Extensive electrical characterization of ring oscillators (ROs) made in high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> metal gate 28-nm fully depleted silicon-on-insulator technology is presented for a set of temperatures between 296 and 4.3 K. First, delay per stage (<inline-formula> <tex-math notation="LaTeX">$\tau _{P}$ </tex-math></inline-formula>), static current (<inline-formula> <tex-math notation="LaTeX">${I} _{\textsf {STAT}}$ </tex-math></inline-formula>), and dynamic current (<inline-formula> <tex-math notation="LaTeX">${I} _{\textsf {DYN}}$ </tex-math></inline-formula>) are analyzed for the case of the increase of threshold voltage (<inline-formula> <tex-math notation="LaTeX">${V} _{\textsf {TH}}$ </tex-math></inline-formula>) observed at low temperature. Then, the same analysis is performed by compensating <inline-formula> <tex-math notation="LaTeX">${V} _{\textsf {TH}}$ </tex-math></inline-formula> to a constant, temperature-independent value through forward body biasing (FBB). Energy efficiency optimization is proposed for different supply voltages (<inline-formula> <tex-math notation="LaTeX">${V} _{\textsf {DD}}$ </tex-math></inline-formula>) in order to find an optimal operating point combining both high RO frequencies and low-power dissipation. We show that the Energy-Delay product can be significantly reduced at low temperature by applying an FBB voltage (<inline-formula> <tex-math notation="LaTeX">${V} _{\textsf {FBB}}$ </tex-math></inline-formula>). We demonstrate that outstanding performance of RO in terms of speed (<inline-formula> <tex-math notation="LaTeX">$\tau _{P} = \textsf {37}$ </tex-math></inline-formula> ps) and static current (7nA/stage) can be achieved at 4.3 K with <inline-formula> <tex-math notation="LaTeX">${V} _{\textsf {DD}}$ </tex-math></inline-formula> reduced down to 0.325 V.

[1]  David Reilly,et al.  Engineering the quantum-classical interface of solid-state qubits , 2015, npj Quantum Information.

[2]  Edoardo Charbon,et al.  Cryo-CMOS Circuits and Systems for Quantum Computing Applications , 2018, IEEE Journal of Solid-State Circuits.

[3]  S. Barraud,et al.  Design and cryogenic operation of a hybrid quantum-CMOS circuit , 2015, 1503.03993.

[4]  Edoardo Charbon,et al.  Impact of Classical Control Electronics on Qubit Fidelity , 2018, Physical Review Applied.

[5]  Robin Wilson,et al.  A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization , 2014, IEEE Journal of Solid-State Circuits.

[6]  E. Simoen,et al.  Chapter 2 – Silicon Devices and Circuits , 2001 .

[7]  Arnout Beckers,et al.  Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing , 2018, 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

[8]  David Blaauw,et al.  Energy-Efficient Subthreshold Processor Design , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  D. DiVincenzo,et al.  Quantum computation with quantum dots , 1997, cond-mat/9701055.

[10]  M. Veldhorst,et al.  Silicon CMOS architecture for a spin-based quantum computer , 2016, Nature Communications.

[11]  O. Rozeau,et al.  28nm FDSOI technology platform for high-speed low-voltage digital applications , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[12]  Guo-Wei Huang,et al.  > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < , 2007 .

[13]  G. Ghibaudo,et al.  Low temperature characterization of 14nm FDSOI CMOS devices , 2014, 2014 11th International Workshop on Low Temperature Electronics (WOLTE).

[14]  E.J. Nowak,et al.  The effective drive current in CMOS inverters , 2002, Digest. International Electron Devices Meeting,.

[15]  Edoardo Charbon,et al.  The Cryogenic Temperature Behavior of Bipolar, MOS, and DTMOS Transistors in Standard CMOS , 2018, IEEE Journal of the Electron Devices Society.

[16]  M. Vinet,et al.  Si CMOS platform for quantum information processing , 2016, 2016 IEEE Symposium on VLSI Technology.

[17]  Lars R. Schreiber,et al.  Quantum computation: Silicon comes back. , 2014, Nature nanotechnology.

[18]  R Maurand,et al.  A CMOS silicon spin qubit , 2016, Nature Communications.

[19]  M. Vinet,et al.  28nm Fully-depleted SOI technology: Cryogenic control electronics for quantum computing , 2017, 2017 Silicon Nanoelectronics Workshop (SNW).

[20]  A. Vladimirescu,et al.  Cryo-CMOS for quantum computing , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[21]  Tsuyoshi Murata,et al.  {m , 1934, ACML.

[22]  J. P. Dehollain,et al.  A two-qubit logic gate in silicon , 2014, Nature.

[23]  Thomas de Quincey.  [C] , 2000, The Works of Thomas De Quincey, Vol. 1: Writings, 1799–1820.

[24]  Olivier Billoint,et al.  UTBB FDSOI technology flexibility for ultra low power internet-of-things applications , 2015, 2015 45th European Solid State Device Research Conference (ESSDERC).

[25]  R. Ishihara,et al.  Interfacing spin qubits in quantum dots and donors—hot, dense, and coherent , 2017, npj Quantum Information.

[26]  Michael L. Schneider,et al.  Ultralow power artificial synapses using nanotextured magnetic Josephson junctions , 2018, Science Advances.

[27]  Edoardo Charbon,et al.  Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures , 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

[28]  Edoardo Charbon,et al.  Performance characterization of Altera and Xilinx 28 nm FPGAs at cryogenic temperatures , 2017, 2017 International Conference on Field Programmable Technology (ICFPT).