Structure-Constrained Microcode Compression

Microcode enables programmability of (micro) architectural structures to enhance functionality and to apply patches to an existing design. As more features get added to a CPU core, the area and power costs associated with microcode increase. One solution to address the microcode size issue is to store the microcode in a compressed form and decompress it during execution. Furthermore, the reuse of a single hardware building block layout to implement different dictionaries in the two-level microcode compression reduces the cost and the design time of the decompression engine. However, the reuse of the hardware building block imposes structural constraints to the compression algorithm, and existing algorithms may yield poor compression. In this paper, we develop the SC2 algorithm that considers the structural constraint in its objective function and reduces the area expansion when reusing hardware building blocks to implement different dictionaries. Our experimental results show that the SC2 algorithm is able to produce similar sized dictionaries and achieves the similar compression ratio to the non-constrained algorithm.

[1]  Joseph A. Fisher,et al.  Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.

[2]  Guido Araujo,et al.  Code compression based on operand factorization , 1998, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture.

[3]  Nagisa Ishiura,et al.  Instruction Code Compression for Application Specific VLIW Processors Based on Automatic Field Partitioning , 2007 .

[4]  Wei Zhao,et al.  Architectural partitioning of control memory for application specific programmable processors , 1995, ICCAD.

[5]  Scott J. Schwartz.  An Algorithm for Minimizing Read Only Memories for Machine Control , 1968, SWAT.

[6]  Trevor N. Mudge,et al.  Improving code density using compression techniques , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[7]  Subrata Dasgupta,et al.  The Organization of Microprogram Stores , 1979, CSUR.

[8]  Trevor N. Mudge,et al.  Evaluation of a high performance code compression method , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.

[9]  Nick Tredennick,et al.  Microprogrammed implementation of a single chip microprocessor , 1978, MICRO 11.

[10]  Ashok K. Agrawala,et al.  Microprogramming: Perspective and Status , 1974, IEEE Transactions on Computers.

[11]  Tibor Gyimóthy,et al.  Survey of code-size reduction methods , 2003, CSUR.

[12]  Guido Araujo,et al.  Clustering-Based Microcode Compression , 2006, 2006 International Conference on Computer Design.

[13]  A. Wolfe,et al.  Executing Compressed Programs On An Embedded RISC Architecture , 1992, [1992] Proceedings the 25th Annual International Symposium on Microarchitecture MICRO 25.

[14]  Onat Menzilcioglu.  A case study in using two-level control stores , 1987, MICRO 20.

[15]  Wayne Wolf,et al.  Compression ratio and decompression overhead tradeoffs in code compression for VLIW architectures , 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

[16]  Mauricio Breternitz,et al.  Enhanced compression techniques to simplify program decompression and execution , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[17]  Fillia Makedon,et al.  Approximation algorithms for VLSI partition problems , 1990, IEEE International Symposium on Circuits and Systems.

[18]  Maurice V. Wilkes,et al.  The best way to design an automatic calculating machine , 1981 .

[19]  Edson Borin.  Microcode compression algorithms , 2007 .