RAM-Based Ultra-Lightweight FPGA Implementation of PRESENT

In this paper, two different FPGA implementations of the lightweight cipher PRESENT are proposed. The main design strategy for both designs is the utilization of existing RAM blocks in FPGAs for the storage of internal states, thereby reducing the slice count. In the first design, S-boxes are realized within the slices, while in the second design they are also integrated into the same RAM block used for state storage. Both designs are well suited for lightweight applications, which are implemented on low-cost FPGA/CPLD devices. Besides low-area, a reasonable throughput is also obtained even though it is not the first concern. In addition to a single block RAM, the two designs occupy only 83 and 85 slices and produce a throughput of 6.03 and 5.13 Kbps at 100 KHz system clock on a Xilinx Spartan XC3S50 device, respectively.

[1]  Jongsung Kim,et al.  HIGHT: A New Block Cipher Suitable for Low-Resource Device , 2006, CHES.

[2]  Willi Meier,et al.  Quark: A Lightweight Hash , 2010, Journal of Cryptology.

[3]  Andrey Bogdanov,et al.  PRESENT: An Ultra-Lightweight Block Cipher , 2007, CHES.

[4]  David E. Culler,et al.  Lessons from a Sensor Network Expedition , 2004, EWSN.

[5]  Jens-Peter Kaps,et al.  Lightweight Cryptography for FPGAs , 2009, 2009 International Conference on Reconfigurable Computing and FPGAs.

[6]  Tim Güneysu,et al.  Generic Side-Channel Countermeasures for Reconfigurable Devices , 2011, CHES.

[7]  Matt Welsh,et al.  Sensor networks for emergency response: challenges and opportunities , 2004, IEEE Pervasive Computing.

[8]  John Anderson,et al.  Wireless sensor networks for habitat monitoring , 2002, WSNA '02.

[9]  Gu-Yeon Wei,et al.  A portable, low-power, wireless two-lead EKG system , 2004, The 26th Annual International Conference of the IEEE Engineering in Medicine and Biology Society.

[10]  Andreas Koch,et al.  Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications , 2011, ARC.

[11]  Amir Moradi,et al.  Side-Channel Resistant Crypto for Less than 2,300 GE , 2011, Journal of Cryptology.

[12]  Steven Trimberger,et al.  A 90-nm Low-Power FPGA for Battery-Powered Applications , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Christof Paar,et al.  Design space exploration of present implementations for FPGAS , 2009, 2009 5th Southern Conference on Programmable Logic (SPL).