Efficient Characterization of Threshold Voltage Instabilities in SiC nMOSFETs Using the Concept of Capture-Emission-Time Maps

We utilize the recently suggested capture-emission-time (CET) maps for the first time for SiC technologies. CET maps are a very powerful characterization technique which allow the elegant and comprehensive analysis of oxide/interface traps at or near the semiconductor-dielectric interface and were originally developed to characterize degradation of Si based MOSFETs. For as-processed SiC MOSFETs we present first results of the SiC-SiO2 interface using CET maps. We suggest that oxide traps are mainly responsible for the instability in SiC MOSFETs. Furthermore we state that the large time constants and the temperature activation of the traps in SiC MOSFETs can be consistently explained when accounting for multi-phonon processes for the microscopic charge exchange. A recently suggested model including such microscopic transitions is applied to SiC MOSFETs and shown to reproduce our experimental data with high accuracy for a large temperature range.

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