Notice of Violation of IEEE Publication PrinciplesTime minimization of hybrid BIST for systems-on-chip

In this paper, we concentrate on hybrid BIST optimization for multi-core designs. As total cost minimization for multi-core systems is an extremely complex problem and is rarely used in reality, the main emphasis here is on test time minimization under memory constraints with different test architectures. The memory constraints can be seen as limitations of on-chip memory or ATE memory, where the deterministic test set will be stored, and therefore with high practical importance. We will concentrate on one large classes of test architectures and we assume that every core is equipped with its own pseudorandom pattern generator and only deterministic patterns have to be transported to the cores. For this architecture we will describe test-per-clock as well as test-per-scan application schemes.