A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers

A 900-MHz monolithic CMOS dual-loop frequency synthesizer suitable for GSM receivers is presented. Implemented in a 0.50-/spl mu/m CMOS technology and at a 2-V supply voltage, the dual-loop frequency synthesizer occupies a chip area of 2.64 mm/sup 2/ and consumes a low power of 34 mW. The measured phase noise of the synthesizer is -121.8 dBc/Hz at 600-kHz offset, and the measured spurious levels are -79.5 and -82.0 dBc at 1.6 and 11.3 MHz offset, respectively.

[1]  J. Long,et al.  The modeling, characterization, and design of monolithic inductors for silicon RF IC's , 1997, IEEE J. Solid State Circuits.

[2]  K. Halonen,et al.  A 2 GHz Phase-Locked Loop Frequency Synthesizer with On-Chip VCO , 1999 .

[3]  Robert G. Meyer,et al.  Start-up and frequency stability in high-frequency oscillators , 1992 .

[4]  Byungsoo Chang,et al.  A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops , 1996 .

[5]  M. Steyaert,et al.  A fully integrated CMOS DCS-1800 frequency synthesizer , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[6]  Christer Svensson,et al.  High-speed CMOS circuit technique , 1989 .

[7]  Michiel Steyaert,et al.  A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors , 1997, IEEE J. Solid State Circuits.

[8]  Keng L. Wong,et al.  A PLL clock generator with 5 to 110 MHz lock range for microprocessors , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[9]  Qiuting Huang,et al.  Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks , 1996 .

[10]  Ali Hajimiri,et al.  A general theory of phase noise in electrical oscillators , 1998 .

[11]  Ali Hajimiri,et al.  Phase noise in multi-gigahertz CMOS ring oscillators , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[12]  Sung Dae Lee,et al.  A high speed and low power phase-frequency detector and charge-pump , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[13]  Hong You,et al.  Optimization of high Q integrated inductors for multi-level metal CMOS , 1995, Proceedings of International Electron Devices Meeting.

[14]  Keng L. Wong,et al.  A PLL clock generator with 5 to 110 MHz of lock range for microprocessors , 1992 .

[15]  J. Khoury,et al.  Advantages of dual-loop frequency synthesizers for GSM applications , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[16]  T.H. Lee,et al.  A 1.5 V, 1.5 GHz CMOS low noise amplifier , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[17]  Christer Svensson,et al.  A true single-phase-clock dynamic CMOS circuit technique , 1987 .

[18]  J. F. Parker,et al.  A 1.6-GHz CMOS PLL with on-chip loop filter , 1998, IEEE J. Solid State Circuits.

[19]  K.K. O,et al.  A 1.24-GHz monolithic CMOS VCO with phase noise of -137 dBc/Hz at a 3-MHz offset , 1999, IEEE Microwave and Guided Wave Letters.

[20]  A. Niknejad,et al.  Analysis , Design , and Optimization of Spiral Inductors and Transformers for Si RF IC ’ s , 1998 .

[21]  Terri S. Fiez,et al.  Analog VLSI : signal and information processing , 1994 .

[22]  P. Larsson High-speed architecture for a programmable frequency divider and a dual-modulus prescaler , 1996 .

[24]  C. Svensson,et al.  Fast CMOS nonbinary divider and counter , 1993 .

[25]  A. Ali,et al.  A 900 MHz frequency synthesizer with integrated LC voltage-controlled oscillator , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.