ADARC: A New Multi-Instruction Issue Approach

The Associative Dataaow Architecture (ADARC) combines features usually associated with either VLIW or with dataaow ar-chitectures to achieve an eecient exploitation of the instruction-level parallelism of numerical algorithms on a modular, scalable, parallel hardware with distributed memory. While the ADARC architecture does not favorize any nal implementation considering the complexity of the used functional units, this paper focuses on a realization which is similar to VLIW-based processors. ADARC extends the synchronous issuing of operations in VLIWs to an asyn-chronous mechanism allowing arbitrary execution times and diier-ent issuing times of the simple instructions out of one VLIW. This new sequencing method is eeciently supported by an intelligent in-terconnection network performing transport triggering mechanisms using associatively controlled switches as routing elements.