A parallel CMOS 2's complement multiplier based on 5:3 counter

A parallel 8/spl times/8 2's complement multiplier based on a novel 5:3 counter is presented. The structure of the multiplier is simple, regular, and very suitable for VLSI implementation. Compared with Wallace tree and Redundant Binary Addition Tree (N. Takagi et al., 1985), the proposed scheme requires less levels for the same number of partial products, resulting in a simpler and faster circuit.<<ETX>>

[1]  Michael J. Flynn,et al.  High-Speed Addition in CMOS , 1992, IEEE Trans. Computers.

[2]  A. R. Cooper.  Parallel architecture modified Booth multiplier , 1988 .

[3]  Mark Horowitz,et al.  SPIM: a pipelined 64*64-bit iterative multiplier , 1989 .

[4]  Hiroto Yasuura,et al.  High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree , 1985, IEEE Transactions on Computers.

[5]  Naofumi Takagi,et al.  Design of high speed MOS multiplier and divider using redundant binary representation , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[6]  S. Sunder.  A fast multiplier based on the modified Booth algorithm , 1993 .

[7]  A. E. A. Almaini,et al.  A simple and high speed CMOS carry chain adder architecture , 1993 .

[8]  Z. Guan.  Logic realization using mixed representations based on Reed-Muller forms , 1994 .

[9]  K. Elleithy,et al.  Fast and flexible architectures for RNS arithmetic decoding , 1992 .

[10]  James E. Robertson,et al.  Logical design of a redundant binary adder , 1978, 1978 IEEE 4th Symposium onomputer Arithmetic (ARITH).

[11]  Luigi Dadda.  Fast multipliers for two's-complement numbers in serial form , 1985, 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH).

[12]  Nick Kanopoulos,et al.  A new serial/parallel two's complement multiplier for vlsi digital signal processing , 1992, Int. J. Circuit Theory Appl..

[13]  D. Radhakrishnan,et al.  Formal design procedures for pass transistor switching circuits , 1985 .

[14]  W. Balakrishnan,et al.  Very-high-speed VLSI 2s-complement multiplier using signed binary digits , 1992 .

[15]  N. Takagi,et al.  A high-speed multiplier using a redundant binary adder tree , 1987 .

[16]  Kazuo Yano,et al.  A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic , 1990 .

[17]  John V. McCanny,et al.  OPTIMISED BIT LEVEL SYSTOLIC ARRAY FOR CONVOLUTION. , 1984 .