Analysis of Quantization Noise Reduction Techniques for Fractional-N PLL

High performance phase-locked loop (PLL) circuits are widely used in wireless communication systems to provide accurate reference for digital modulation and demodulation. It has large applications in electronic devices such as cell phones, remote control devices, laptops, and alarm systems. Usually a simple integer-N PLL consists of phase-frequency detector (PFD), charge pump, loop filter, VCO, and divider. One drawback of integer-N PLL is that its frequency resolution is limited to the operating frequency of PFD. Unlike integer-N PLL, fractional-N PLL can achieve a frequency step much smaller than its reference and thus has a wider loop bandwidth while achieving very high frequency resolution. However, the usage of fractional control module in a fractional-N PLL will produce quantization noise and spurs at PLL output, which deteriorates the phase noise performance of the synthesized clock.