论文信息 - Design, simulation and process optimization of AuInSn low temperature TLP bonding for 3D IC Stacking - 字舞流文

Design, simulation and process optimization of AuInSn low temperature TLP bonding for 3D IC Stacking

Siong Chiew Ong | V. N. Sekhar | C. Selvanayagam | C. Premachandran | Yingzhi Zeng | K. Bai | E. Liao | W. Choi | A. Khairyanto | Ling Xie | S. Thew