Automated data analysis techniques for a modern silicon debug environment

With the growing size of modern designs and more strict time-to-market constraints, design errors unavoidably escape pre-silicon verification and reside in silicon prototypes. As a result, silicon debug has become a necessary step in the digital integrated circuit design flow. Although embedded hardware blocks, such as scan chains and trace buffers, provide a means to acquire data of internal signals in real time for debugging, there is a relative shortage in methodologies to efficiently analyze this vast data to identify root-causes. This paper presents an automated software solution that attempts to fill-in the gap. The presented techniques automate the configuration process for trace-buffer based hardware in order to acquire helpful information for debugging the failure, and detect suspects of the failure in both the spatial and temporal domain.

[1]  Karem A. Sakallah,et al.  GRASP—a new search algorithm for satisfiability , 1996, ICCAD 1996.

[2]  Nicola Nicolici,et al.  Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Bashir M. Al-Hashimi,et al.  Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Rolf Drechsler,et al.  Post-verification debugging of hierarchical designs , 2005, ICCAD 2005.

[5]  Kwang-Ting Cheng,et al.  Safety property verification using sequential SAT and bounded model checking , 2004, IEEE Design & Test of Computers.

[6]  Nur A. Touba,et al.  Automated Selection of Signals to Observe for Efficient Silicon Debug , 2009, 2009 27th IEEE VLSI Test Symposium.

[7]  Qiang Xu,et al.  Trace signal selection for visibility enhancement in post-silicon validation , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[8]  Tracy Larrabee,et al.  Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Michael Miller,et al.  Emulation verification of the Motorola 68060 , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[10]  Masahiro Fujita,et al.  Modeling the unknown! Towards model-independent fault and error diagnosis , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[11]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[12]  Sharad Malik,et al.  On Solving the Partial MAX-SAT Problem , 2006, SAT.

[13]  Niklas Sörensson,et al.  An Extensible SAT-solver , 2003, SAT.

[14]  Alberto L. Sangiovanni-Vincentelli,et al.  A survey of techniques for formal verification of combinational circuits , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[15]  Andreas G. Veneris,et al.  Automated data analysis solutions to silicon debug , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[16]  Joao Marques-Silva,et al.  GRASP-A new search algorithm for satisfiability , 1996, Proceedings of International Conference on Computer Aided Design.

[17]  Andreas G. Veneris,et al.  Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Kai Yang,et al.  Diagnosing Silicon Failures Based on Functional Test Patterns , 2006, Seventh International Workshop on Microprocessor Test and Verification (MTV'06).

[19]  Qiang Xu,et al.  On Signal Selection for Visibility Enhancement in Trace-Based Post-Silicon Validation , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Alan J. Hu,et al.  BackSpace: Formal Analysis for Post-Silicon Debug , 2008, 2008 Formal Methods in Computer-Aided Design.

[21]  Ismet Bayraktaroglu,et al.  Microprocessor silicon debug based on failure propagation tracing , 2005, IEEE International Conference on Test, 2005..

[22]  Andreas G. Veneris.  Fault diagnosis and logic debugging using Boolean satisfiability , 2003, Proceedings. 4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions.

[23]  Joao Marques-Silva,et al.  GRASP: A Search Algorithm for Propositional Satisfiability , 1999, IEEE Trans. Computers.

[24]  Sean Safarpour,et al.  Automated silicon debug data analysis techniques for a hardware data acquisition environment , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[25]  W. Kent Fuchs,et al.  A deductive technique for diagnosis of bridging faults , 1997, ICCAD 1997.

[26]  Sharad Malik,et al.  Toward formalizing a validation methodology using simulation coverage , 1997, DAC.