SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms

This paper presents SPHERE, a project aimed at the realization of an integrated framework to abstract the hardware complexity of interconnected, modern system-on-chips (SoC) and simplify the management of their heterogeneous computational resources. The SPHERE framework leverages hypervisor technology to virtualize computational resources and isolate the behavior of different subsystems running on the same platform, while providing safety, security, and real-time communication mechanisms. The main challenges addressed by SPHERE are discussed in the paper along with a set of new technologies developed in the context of the project. They include isolation mechanisms for mixed-criticality applications, predictable I/O virtualization, the management of time-sensitive networks with heterogeneous traffic flows, and the management of field-programmable gate arrays (FPGA) to provide efficient implementations for cryptography modules, as well as hardware acceleration for deep neural networks. The SPHERE architecture is validated through an autonomous driving use-case.

[1]  Silviu S. Craciunas,et al.  Window-Based Schedule Synthesis for Industrial IEEE 802.1Qbv TSN Networks , 2020, 2020 16th IEEE International Conference on Factory Communication Systems (WFCS).

[2]  Paolo Valente,et al.  Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems , 2019, 2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS).

[3]  Giorgio C. Buttazzo,et al.  A Framework for Supporting Real-Time Applications on Dynamic Reconfigurable FPGAs , 2016, 2016 IEEE Real-Time Systems Symposium (RTSS).

[4]  Lucia Lo Bello.  Novel trends in automotive networks: A perspective on Ethernet and the IEEE Audio Video Bridging , 2014, Proceedings of the 2014 IEEE Emerging Technology and Factory Automation (ETFA).

[5]  Takashi Nakada,et al.  Efficient Multitasking on FPGA Using HDL-Based Checkpointing , 2018, ARC.

[6]  Darshika G. Perera,et al.  Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices , 2020, IEEE Access.

[7]  Dengguo Feng,et al.  Stream cipher designs: a review , 2020, Science China Information Sciences.

[8]  Qiang Wang,et al.  Formal Analysis of TSN Scheduler for Real-Time Communications , 2021, IEEE Transactions on Reliability.

[9]  Giorgio Buttazzo,et al.  Supporting temporal and spatial isolation in a hypervisor for ARM multicore platforms , 2018, 2018 IEEE International Conference on Industrial Technology (ICIT).

[10]  Ismael Ripoll,et al.  Partitioned Embedded Architecture Based on Hypervisor: The XtratuM Approach , 2010, 2010 European Dependable Computing Conference.

[11]  Nicola Capodieci,et al.  System Performance Modelling of Heterogeneous HW Platforms: An Automated Driving Case Study , 2019, 2019 22nd Euromicro Conference on Digital System Design (DSD).

[12]  Marko Bertogna,et al.  A Systematic Assessment of Embedded Neural Networks for Object Detection , 2020, 2020 25th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA).

[13]  Sebastian Thrun,et al.  Robust vehicle localization in urban environments using probabilistic maps , 2010, 2010 IEEE International Conference on Robotics and Automation.

[14]  Lui Sha,et al.  MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms , 2013, 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS).

[15]  Sungkwon Park,et al.  Time-Sensitive Network (TSN) Experiment in Sensor-Based Integrated Environment for Autonomous Driving , 2019, Sensors.

[16]  Lucia Lo Bello,et al.  Schedulability analysis of Time-Sensitive Networks with scheduled traffic and preemption support , 2020, J. Parallel Distributed Comput..

[17]  Giorgio Buttazzo,et al.  AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC , 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

[18]  Cuauhtemoc Mancillas-López,et al.  Secure Internal Communication of a Trustzone-Enabled Heterogeneous Soc Lightweight Encryption , 2019, 2019 International Conference on Field-Programmable Technology (ICFPT).

[19]  Lucia Lo Bello,et al.  Towards Time-Sensitive Networking in Heterogeneous Platforms with Virtualization , 2020, 2020 25th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA).

[20]  Ali Farhadi,et al.  You Only Look Once: Unified, Real-Time Object Detection , 2015, 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR).

[21]  Wolfgang Mauerer,et al.  Look Mum, no VM Exits! (Almost) , 2017, ArXiv.

[22]  Silviu S. Craciunas,et al.  Scheduling Real-Time Communication in IEEE 802.1Qbv Time Sensitive Networks , 2016, RTNS.

[23]  Massimo Torquati,et al.  Single-Producer/Single-Consumer Queues on Shared Cache Multi-Core Systems , 2010, ArXiv.

[24]  Wilfried Steiner,et al.  A Perspective on IEEE Time-Sensitive Networking for Industrial Communication and Automation Systems , 2019, Proceedings of the IEEE.

[25]  Daniel Hallmans,et al.  Analysis of the TSN Standards for Utilization in Long-life Industrial Distributed Control Systems , 2020, 2020 25th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA).

[26]  Rodolfo Pellizzoni,et al.  A Survey on Cache Management Mechanisms for Real-Time Embedded Systems , 2015, ACM Comput. Surv..

[27]  Giorgio Buttazzo,et al.  Latency Analysis of I/O Virtualization Techniques in Hypervisor-Based Real-Time Systems , 2021, 2021 IEEE 27th Real-Time and Embedded Technology and Applications Symposium (RTAS).

[28]  Geoffrey Nelissen,et al.  A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling , 2020, 2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS).

[29]  Giuliana Alderisi,et al.  Schedulability analysis of Ethernet Audio Video Bridging networks with scheduled traffic support , 2017, Real-Time Systems.

[30]  Giorgio C. Buttazzo,et al.  A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration , 2017, 2017 30th IEEE International System-on-Chip Conference (SOCC).