Identifying the sources of unpredictability in COTS-based multicore systems

COTS-based multicores are now the preferred choice for hosting embedded applications owing to their immense computational capabilities, small form factor and low power consumption. Many of these embedded applications have real-time requirements and real-time system designers must be able assess them for their predictability and provide guarantees (at design time) that they deliver the correct functional behavior within predefined time bounds. However, the underlying architecture of commercially available multicores is extremely complex and non-amenable to straight-forward timing analysis. In this paper, we highlight the architectural features leading to temporal unpredictability, which mainly involve shared hardware resources, such as buses, caches, and memories. We explore some of the existing work in timing analysis with respect to these features, identify their limitations, and present some unaddressed issues that must be dealt with to ensure safe deployment of real-time systems.

[1]  Jun Shao,et al.  A Burst Scheduling Access Reordering Mechanism , 2007, 2007 IEEE 13th International Symposium on High Performance Computer Architecture.

[2]  Jan Reineke,et al.  Timing predictability of cache replacement policies , 2007, Real-Time Systems.

[3]  Kelvin D. Nilsen,et al.  Cache Issues in Real-Time Systems , 1994 .

[4]  Frank Mueller,et al.  Tightening the bounds on feasible preemptions , 2011, TECS.

[5]  Reinhard Wilhelm,et al.  The influence of processor architecture on the design and the results of WCET tools , 2003, Proceedings of the IEEE.

[6]  Peter Marwedel,et al.  Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds , 2011, 2011 23rd Euromicro Conference on Real-Time Systems.

[7]  Francisco J. Cazorla,et al.  An Analyzable Memory Controller for Hard Real-Time CMPs , 2009, IEEE Embedded Systems Letters.

[8]  Peter Davies,et al.  The TLB slice-a low-cost high-speed address translation mechanism , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.

[9]  Alberto L. Sangiovanni-Vincentelli,et al.  Moving From Federated to Integrated Architectures in Automotive: The Role of Standards, Methods and Tools , 2010, Proceedings of the IEEE.

[10]  Rolf Ernst,et al.  A bandwidth optimized SDRAM controller for the MORPHEUS reconfigurable architecture , 2008, 2008 IEEE International Symposium on Parallel and Distributed Processing.

[11]  Artur Burchard,et al.  A real-time streaming memory controller , 2005, Design, Automation and Test in Europe.

[12]  Anthony Rowe,et al.  FireFly Mosaic: A Vision-Enabled Wireless Sensor Networking System , 2007, RTSS 2007.

[13]  Wang Yi,et al.  Multicore Embedded Systems: The Timing Problem and Possible Solutions , 2010, ICFEM.

[14]  Peter Davies,et al.  The TLB slice—a low-cost high-speed address translation mechanism , 1990, ISCA '90.

[15]  John W. Lockwood,et al.  Beyond performance: secure and fair memory management for multiple systems on a chip , 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).

[16]  Bruce Jacob,et al.  Memory Systems: Cache, DRAM, Disk , 2007 .

[17]  Flavius Gruian,et al.  System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors , 2000, PACS.

[18]  Wei Zhang,et al.  WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches , 2008, 2008 IEEE Real-Time and Embedded Technology and Applications Symposium.

[19]  Raymond R. Devillers,et al.  Power-Aware Real-Time Scheduling upon Identical Multiprocessor Platforms , 2008, 2008 IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing (sutc 2008).

[20]  Jakob Engblom,et al.  The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.

[21]  Lothar Thiele,et al.  Design for Time-Predictability , 2004, Design of Systems with Predictable Behaviour.

[22]  Alexandra Fedorova,et al.  Addressing shared resource contention in multicore processors via scheduling , 2010, ASPLOS XV.

[23]  Onur Mutlu,et al.  Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Shared Memory Controllers , 2009, IEEE Micro.

[24]  Damien Hardy,et al.  Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches , 2009, 2009 30th IEEE Real-Time Systems Symposium.

[25]  Tei-Wei Kuo,et al.  Multiprocessor energy-efficient scheduling with task migration considerations , 2004, Proceedings. 16th Euromicro Conference on Real-Time Systems, 2004. ECRTS 2004..

[26]  Tulika Mitra,et al.  Exploring locking & partitioning for predictable shared caches on multi-cores , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[27]  Mahmut T. Kandemir,et al.  Thermal-aware task allocation and scheduling for embedded systems , 2005, Design, Automation and Test in Europe.

[28]  Vincent Nélis,et al.  An Analysis of the Impact of Bus Contention on the WCET in Multicores , 2012, 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems.

[29]  Stephen P. Boyd,et al.  Temperature-aware processor frequency assignment for MPSoCs using convex optimization , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[30]  Jan Reineke,et al.  Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[31]  Mahmut T. Kandemir,et al.  Hardware and Software Techniques for Controlling DRAM Power Modes , 2001, IEEE Trans. Computers.

[32]  Tulika Mitra,et al.  Modeling shared cache and bus in multi-cores for timing analysis , 2010, SCOPES.

[33]  C.B. Watkins,et al.  Transitioning from federated avionics architectures to Integrated Modular Avionics , 2007, 2007 IEEE/AIAA 26th Digital Avionics Systems Conference.

[34]  Rolf Ernst,et al.  Bounding the shared resource load for the performance analysis of multiprocessor systems , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[35]  Vincent Nélis,et al.  MORA: An Energy-Aware Slack Reclamation Scheme for Scheduling Sporadic Real-Time Tasks upon Multiprocessor Platforms , 2009, 2009 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications.

[36]  Kees G. W. Goossens,et al.  Architectures and modeling of predictable memory controllers for improved system integration , 2011, 2011 Design, Automation & Test in Europe.

[37]  Petru Eles,et al.  Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip , 2007, 28th IEEE International Real-Time Systems Symposium (RTSS 2007).

[38]  Edward A. Lee,et al.  PRET DRAM controller: Bank privatization for predictability and temporal isolation , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[39]  Lui Sha,et al.  Memory Access Control in Multiprocessor for Real-Time Systems with Mixed Criticality , 2012, 2012 24th Euromicro Conference on Real-Time Systems.

[40]  Dar-Biau Liu,et al.  Component-based systems development: challenges and lessons learned , 1997, Proceedings Eighth IEEE International Workshop on Software Technology and Engineering Practice incorporating Computer Aided Software Engineering.

[41]  Xiaobo Sharon Hu,et al.  Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[42]  Lothar Thiele,et al.  Timing Analysis for TDMA Arbitration in Resource Sharing Systems , 2010, 2010 16th IEEE Real-Time and Embedded Technology and Applications Symposium.

[43]  James H. Anderson,et al.  Cache-Aware Real-Time Scheduling on Multicore Platforms: Heuristics and a Case Study , 2008, 2008 Euromicro Conference on Real-Time Systems.

[44]  Kees G. W. Goossens,et al.  Conservative open-page policy for mixed time-criticality memory controllers , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[45]  R. Bell,et al.  IEC 61508: functional safety of electrical/electronic/ programme electronic safety-related systems: overview , 1999 .

[46]  Hennadiy Leontyev,et al.  Accounting for Interrupts in Multiprocessor Real-Time Systems , 2009, 2009 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications.

[47]  Lothar Thiele,et al.  Design for Timing Predictability , 2004, Real-Time Systems.

[48]  Reinhold Heckmann,et al.  Static Memory and Timing Analysis of Embedded Systems Code , 2006 .

[49]  Lothar Thiele,et al.  Thermal-Aware Global Real-Time Scheduling on Multicore Systems , 2009, 2009 15th IEEE Real-Time and Embedded Technology and Applications Symposium.

[50]  Lothar Thiele,et al.  Worst case delay analysis for memory interference in multicore systems , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[51]  Neil C. Audsley,et al.  Predictable and efficient virtual addressing for safety-critical real-time systems , 2001, Proceedings 13th Euromicro Conference on Real-Time Systems.

[52]  Xiaobo Sharon Hu,et al.  Task scheduling and voltage selection for energy minimization , 2002, DAC '02.

[53]  Sangyeun Cho,et al.  Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems , 2007, 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007).

[54]  M. Caccamo,et al.  Using Multicore Architectures in Cyber-Physical Systems , 2011 .

[55]  Björn Andersson,et al.  Response Time Analysis of COTS-Based Multicores Considering the Contention on the Shared Memory Bus , 2011, 2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications.

[56]  Björn Lisper,et al.  Towards WCET Analysis of Multicore Architectures Using UPPAAL , 2010, WCET.

[57]  Lothar Thiele,et al.  Timing Analysis for Resource Access Interference on Adaptive Resource Arbiters , 2011, 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium.

[58]  Tei-Wei Kuo,et al.  Leakage-Aware Energy-Efficient Scheduling of Real-Time Tasks in Multiprocessor Systems , 2006, 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06).

[59]  Chin-Fu Kuo,et al.  Energy-Efficient Scheduling for Real-Time Systems on Dynamic Voltage Scaling (DVS) Platforms , 2007, 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007).

[60]  William J. Dally,et al.  Memory access scheduling , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[61]  Ahr Rob Albers,et al.  Memory-communication model for low-latency X-ray video processing on multiple cores , 2009 .

[62]  Yun Liang,et al.  Timing analysis of concurrent programs running on shared cache multi-cores , 2009, 2009 30th IEEE Real-Time Systems Symposium.

[63]  Reinhard Wilhelm,et al.  Efficient and Precise Cache Behavior Prediction for Real-Time Systems , 1999, Real-Time Systems.

[64]  Rami G. Melhem,et al.  Energy aware scheduling for distributed real-time systems , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[65]  Chein-Wei Jen,et al.  An efficient quality-aware memory controller for multimedia platform SoC , 2005, IEEE Transactions on Circuits and Systems for Video Technology.

[66]  Kees G. W. Goossens,et al.  A Predictor-Based Power-Saving Policy for DRAM Memories , 2012, 2012 15th Euromicro Conference on Digital System Design.

[67]  Wang Yi,et al.  Cache-aware scheduling and analysis for multicores , 2009, EMSOFT '09.

[68]  Rolf Ernst,et al.  Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[69]  Andreas Ermedahl,et al.  A Modular Tool Architecture for Worst-Case Execution Time Analysis , 2008 .