Ultra-low-voltage design of nanometer CMOS circuits for smart energy-autonomous systems

The success of the semiconductor industry today owes a lot to high-volume products for consumer applications such as smart phones and laptop computers. However, there exist other categories of applications with different requirements in terms of processing capability, power consumption, and usability. Among them, energy-autonomous systems (EAS) is a primising application category. An EAS is defined as "an electronic system that has been designed to operate and/or communicate as long as possible in known/unknown environments providing, elaborating and storing information without being connected to a power grid" [4]. As EAS are not connected to a power grid, they either operate on a tiny battery with limited energy storage or harvest energy from their environment. Commercial EAS applications are mainly passive/active RFID tags, biomedical devices, and basic wireless sensors for industrial or habitat monitoring. On the research side, EAS have been studied for a while and recent system demonstration include new exciting applications such as biomedical implants [18, 20, 41, 68]. eHealth devices [31, 35, 39, 54, 59], body-area networks [38, 40], nearly-perpetual environmental sensing [17], and insect motion control [21].

[1]  David Bol,et al.  Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits , 2010, 2010 Proceedings of ESSCIRC.

[2]  Paolo Fiorini,et al.  Energy autonomous systems : future trends in devices, technology, and systems , 2009 .

[3]  David Bol,et al.  Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic , 2009, ISLPED.

[4]  Stuart N. Wooters,et al.  A 2.6-µW sub-threshold mixed-signal ECG SoC , 2009, 2009 Symposium on VLSI Circuits.

[5]  David Bol,et al.  The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic , 2010, 2010 Proceedings of ESSCIRC.

[6]  David Bol,et al.  Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits , 2009, ISLPED.

[7]  D. Flandre,et al.  Roadmap for nanometer ultra-low-power digital circuits based on sub / near-threshold CMOS logic , 2009 .

[8]  David Bol,et al.  Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic---Mitigation at Technology and Circuit Levels , 2010, TODE.

[9]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.

[10]  Sudipto Chakraborty,et al.  Mixed-signal integrated circuits for self-contained sub-cubic millimeter biomedical implants , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[11]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[12]  Seulki Lee,et al.  A 75μW real-time scalable network controller and a 25μW ExG sensor IC for compact sleep-monitoring applications , 2011, 2011 IEEE International Solid-State Circuits Conference.

[13]  B.C. Paul,et al.  Device optimization for digital subthreshold logic operation , 2005, IEEE Transactions on Electron Devices.

[14]  Bo Zhai,et al.  A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[15]  David Blaauw,et al.  Circuits for a Cubic-Millimeter Energy-Autonomous Wireless Intraocular Pressure Monitor , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  David Blaauw,et al.  Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[17]  Kaushik Roy,et al.  Analysis of Super Cut-off Transistors for Ultralow Power Digital Logic Circuits , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

[18]  David Blaauw,et al.  Clock network design for ultra-low power applications , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

[19]  A.P. Chandrakasan,et al.  A 65 nm Sub-$V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter , 2008, IEEE Journal of Solid-State Circuits.

[20]  Yeong-Ray Wen,et al.  Pain Control on Demand Based on Pulsed Radio-Frequency Stimulation of the Dorsal Root Ganglion Using a Batteryless Implantable CMOS SoC , 2010, IEEE Transactions on Biomedical Circuits and Systems.

[21]  Kaushik Roy,et al.  Ultra-low-power DLMS adaptive filter for hearing aid applications , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[22]  A.P. Chandrakasan,et al.  Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits , 2008, IEEE Transactions on Electron Devices.

[23]  Denis C. Daly,et al.  A Pulsed UWB Receiver SoC for Insect Motion Control , 2010, IEEE Journal of Solid-State Circuits.

[24]  David Ruffieux,et al.  A 1V RF SoC with an 863-to-928MHz 400kb/s radio and a 32b Dual-MAC DSP core for Wireless Sensor and Body Networks , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[25]  David Blaauw,et al.  Statistical Timing Analysis: From Basic Principles to State of the Art , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  Yu Cao,et al.  Mapping statistical process variations toward circuit performance variability: an analytical modeling approach , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[27]  Andrew R. Brown,et al.  Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs , 2003 .

[28]  Kaushik Roy,et al.  High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness , 2000, Proceedings 2000 International Conference on Computer Design.

[29]  E.J. Nowak,et al.  Improved effective switching current (IEFF+) and capacitance methodology for CMOS circuit performance prediction and model-to-hardware correlation , 2008, 2008 IEEE International Electron Devices Meeting.

[30]  David Bol,et al.  Interests and Limitations of Technology Scaling for Subthreshold Logic , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[31]  M. Woo,et al.  Low cost 65nm CMOS platform for Low Power & General Purpose applications , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[32]  Kaushik Roy,et al.  ABRM: Adaptive $ \beta$-Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[33]  Yajun Ha,et al.  An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage , 2010, IEEE Journal of Solid-State Circuits.

[34]  H. De Man,et al.  Ambient intelligence: gigascale dreams and nanoscale realities , 2005 .

[35]  K. Roy,et al.  Underlap DGMOS for digital-subthreshold operation , 2006, IEEE Transactions on Electron Devices.

[36]  Yong Lian,et al.  A 1V 22µW 32-channel implantable EEG recording IC , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[37]  J. Jopling,et al.  High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[38]  Refet Firat Yazicioglu,et al.  A low power ECG signal processor for ambulatory arrhythmia monitoring system , 2010, 2010 Symposium on VLSI Circuits.

[39]  T. Skotnicki,et al.  Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia , 2008, IEEE Transactions on Electron Devices.

[40]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[41]  O. Rozeau,et al.  High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding , 2008, 2008 IEEE International Electron Devices Meeting.

[42]  Nisha Checka,et al.  FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics , 2010, Proceedings of the IEEE.

[43]  Mingoo Seok,et al.  Nanometer Device Scaling in Subthreshold Logic and SRAM , 2008, IEEE Transactions on Electron Devices.

[44]  You-Yin Chen,et al.  A programmable implantable micro-stimulator SoC with wireless telemetry: Application in closed-loop endocardial stimulation for cardiac pacemaker , 2011, 2011 IEEE International Solid-State Circuits Conference.

[45]  T. Fukai,et al.  Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies , 2007, 2007 IEEE International Electron Devices Meeting.

[46]  Anantha P. Chandrakasan,et al.  A Micro-power EEG acquisition SoC with integrated seizure detection processor for continuous patient monitoring , 2009, 2009 Symposium on VLSI Circuits.

[47]  David Bol,et al.  Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags , 2011, Journal of Cryptographic Engineering.

[48]  S. Narendra,et al.  Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors , 2003 .

[49]  David Bol Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS , 2011 .

[50]  David Bol,et al.  Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[51]  David Blaauw,et al.  Analysis and mitigation of variability in subthreshold design , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[52]  A. Wang,et al.  Modeling and sizing for minimum energy operation in subthreshold circuits , 2005, IEEE Journal of Solid-State Circuits.

[53]  Kaushik Roy,et al.  Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era , 2010, Proceedings of the IEEE.

[54]  David Bol,et al.  Analysis and minimization of practical energy in 45nm subthreshold logic circuits , 2008, 2008 IEEE International Conference on Computer Design.

[55]  K. Roy,et al.  Double gate-MOSFET subthreshold circuit for ultralow power applications , 2004, IEEE Transactions on Electron Devices.

[56]  Anantha Chandrakasan,et al.  A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder , 2009, IEEE Journal of Solid-State Circuits.

[57]  J. Fellrath,et al.  CMOS analog integrated circuits based on weak inversion operations , 1977 .

[58]  Anantha Chandrakasan,et al.  A 0.4-V UWB baseband processor , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[59]  David Bol,et al.  Channel Length Upsize for Robust and Compact Subthreshold SRAM , 2008 .

[60]  David Bol,et al.  Assessment of 65nm subthreshold logic for smart RFID applications , 2009 .

[61]  Seok-Jun Lee,et al.  Microwatt embedded processor platform for medical system-on-chip applications , 2010, 2010 Symposium on VLSI Circuits.

[62]  D. Flandre,et al.  Sub-45nm fully-depleted SOI CMOS subthreshold logic for ultra-low-power applications , 2008, 2008 IEEE International SOI Conference.

[63]  Anantha Chandrakasan,et al.  Variation-Driven Device Sizing for Minimum Energy Sub-threshold Circuits , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

[64]  Kaushik Roy,et al.  Ultra-low power digital subthreshold logic circuits , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[65]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[66]  Bo Zhai,et al.  Exploring Variability and Performance in a Sub-200-mV Processor , 2008, IEEE Journal of Solid-State Circuits.

[67]  L. H. Vanamurth,et al.  Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[68]  Gu-Yeon Wei,et al.  Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations , 2006, CASES '06.