Turnus: A unified dataflow design space exploration framework for heterogeneous parallel systems

This paper presents the main features of the TURNUS co-exploration environment, an unified design space exploration framework suitable for heterogeneous parallel systems designed using an high level dataflow representation. The main functions of this tool are illustrated through the analysis of a video decoder implemented in the RVC-CAL dataflow language.

[1]  Claudio Alberti,et al.  Representing Guard Dependencies in Dataflow Execution Traces , 2013, 2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks.

[2]  Ghislain Roquier,et al.  Synthesizing hardware from dataflow programs: An MPEG-4 simple profile decoder case study , 2008, SiPS.

[3]  Edward A. Lee,et al.  Dataflow process networks , 1995, Proc. IEEE.

[4]  Sandeep K. Shukla,et al.  Dataflow Architectures for GALS , 2008, Electron. Notes Theor. Comput. Sci..

[5]  Jorn W. Janneck,et al.  Synthesis and optimization of high-level stream programs , 2013, Proceedings of the 2013 Electronic System Level Synthesis Conference (ESLsyn).

[6]  Jörn W. Janneck,et al.  Buffer optimization based on critical path analysis of a dataflow program design , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[7]  Marco Mattavelli,et al.  High-abstraction level complexity analysis and memory architecture simulations of multimedia algorithms , 2005, IEEE Transactions on Circuits and Systems for Video Technology.

[8]  Claudio Alberti,et al.  Partitioning and optimization of high level stream applications for multi clock domain architectures , 2013, SiPS 2013 Proceedings.

[9]  Gilles Kahn,et al.  The Semantics of a Simple Language for Parallel Programming , 1974, IFIP Congress.

[10]  Jörn W. Janneck,et al.  Profiling of Dataflow Programs Using Post Mortem Causation Traces , 2012, 2012 IEEE Workshop on Signal Processing Systems.

[11]  Jack B. Dennis,et al.  First version of a data flow procedure language , 1974, Symposium on Programming.

[12]  Claudio Alberti,et al.  Design space exploration of high level stream programs on parallel architectures: A focus on the buffer size minimization and optimization problem , 2013, 2013 8th International Symposium on Image and Signal Processing and Analysis (ISPA).

[13]  Ghislain Roquier,et al.  High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms , 2010, 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP).

[14]  Praveen K. Murthy,et al.  Memory Management for Synthesis of DSP Software , 2006 .

[15]  Ulrik Brandes,et al.  Graph Markup Language (GraphML) , 2013, Handbook of Graph Drawing and Visualization.

[16]  Ghislain Roquier,et al.  Software Code Generation for the RVC-CAL Language , 2011, J. Signal Process. Syst..

[17]  J.-F. Nezan,et al.  Reconfigurable video coding on multicore , 2009, IEEE Signal Processing Magazine.

[18]  Ghislain Roquier,et al.  High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms , 2013, Journal of Real-Time Image Processing.

[19]  Maxime Pelcat,et al.  A System-Level Architecture Model for Rapid Prototyping of Heterogeneous Multicore Embedded Systems , 2009 .

[20]  K. Keutzer,et al.  System-level design: orthogonalization of concerns andplatform-based design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Ghislain Roquier,et al.  Methods to explore design space for MPEG RMC codec specifications , 2013, Signal Process. Image Commun..

[22]  Jörn W. Janneck,et al.  Profiling dataflow programs , 2008, 2008 IEEE International Conference on Multimedia and Expo.