A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI

We had reported TTRAM (Morishita, 2005) and ET2RAM (Arimoto, 2006) which are high-density capacitor-less SOI-CMOS compatible memory IP's. A platform design methodology becomes the main stream in SoC world because the system integration progress and complexity requires the implementation of many lands of IP's and induces the longer design turn around time and design cost up. This time, we have up-graded ET2RAM with scalable function named SETRAM (scalable enhanced twin-transistor RAM). This memory IP can be applied to the many kinds of applications by the verify control technique with compact ABC (automatic body control) sense amplifier. The scalable functions are, for example, 263MHz high speed random cycle memory to replace the high density on chip SRAM, 79mW/4Mb lower active power dissipation for mobile application, 453MHz data transfer of page/burst mode for cache memory and graphics memory applications and lower stand-by current mode of 5 sec data retention time. These are also supported as the programmable functions. The SETRAM can provide the scalable memory IP's in SoC platform on SOI devices and can improve the performance of many future applications