Architectural integration of rf-interconnect to enhance on-chip communication for many-core chip multiprocessors

As the number of cores integrated onto a die increases, the potential for increased throughput exists, as work can be decomposed into parallel tasks and divided among the computing elements. However, the communication architecture between cores must handle an increase in bandwidth demand, as the total traffic on the interconnection network scales with the number of active processor cores and cache banks. Poor wire scaling has complicated things further, leading to increased latency cost of communication between distant points on the die. This motivates our investigation of advanced interconnect architectures aimed at reducing on-chip memory-access latency as well as network power consumption. RF-Interconnect (RF-I) is a low-latency, low-power, high-bandwidth signaling technology projected to scale better than both conventional wires or competing transmission line technologies. In this dissertation, we present the first on-chip interconnection network which utilizes RF-I technology as an overlay upon a conventional wire mesh topology, logically behaving as a set of express-channels (or shortcuts) between distant end-points on the chip. Assuming a 400mm2 (lie, we have demonstrated that in exchange for 0.18% of area overhead on the active layer, RF-I can provide an average 13% (max 18%) boost in application performance, corresponding to an average 22% (max 24%) reduction in packet latency. We have also observed that the patterns of core-to-core and core-to-cache communication may vary over the course of an application's execution as well as within an application. Informed by these findings, we have employed dynamically adaptive RF-I shortcuts in our topology, which provide communication bandwidth only where and when required. Furthermore, we reduce overall network power-consumption by reducing bandwidth of the baseline mesh links, substituting RF-I for conventional-wire to realize an overall power and performance gain. We demonstrate that this overall strategy can enable a 65% NoC power savings as well as an 82.3% NoC area savings, with a simultaneous performance gain of 1%. Finally, we demonstrate that even under ideal conditions, there is no significant performance nor power advantage to adapting RF-I shortcuts more frequently than once per application.