Accurate piecewise uniform approximation logarithmic/antilogarithmic converters for GPU applications

Logarithmic number system (LNS) is increasingly used for low power arithmetic calculations in graphical processing unit (GPU). LNS requires less hardware. Based on uniform subdivisions and linear-Lagrange interpolation, a novel 8-subdivisions logarithmic/antilogarithmic converters are proposed. Compared with different methodologies, the proposed logarithmic/antilogarithmic converters achieve high accuracy. Also, a significant decrease in area is presented in the comparison between the proposed converters and the prior ones. Hardware implementation using shift-and-add approach is adopted to further simplify the hardware. The novel logarithmic/antilogarithmic converters are implemented and synthesized using 90 nm CMOS technology. Up to 23% and 11% decrease in relative error and area are achieved.

[1]  S. L. SanGregory,et al.  A fast, low-power logarithm approximation with CMOS VLSI implementation , 1999, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356).

[2]  Khalid H. Abed,et al.  VLSI Implementation of a Low-Power Antilogarithmic Converter , 2003, IEEE Trans. Computers.

[3]  Magdy A. El-Moursy,et al.  Double Logarithmic Arithmetic Technique for Low-Power 3-D Graphics Applications , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Behrooz Parhami,et al.  A logarithmic approach to energy-efficient GPU arithmetic for mobile devices , 2013, 2013 Asilomar Conference on Signals, Systems and Computers.

[5]  Khalid H. Abed,et al.  CMOS VLSI Implementation of a Low-Power Logarithmic Converter , 2003, IEEE Trans. Computers.

[6]  Shen-Fu Hsiao,et al.  Design of a low-cost floating-point programmable vertex processor for mobile graphics applications based on hybrid number system , 2011, 2011 IEEE International Conference on IC Design & Technology.

[7]  R. Rachel Selina,et al.  VLSI implementation of Piecewise Approximated antilogarithmic converter , 2013, 2013 International Conference on Communication and Signal Processing.

[8]  Chao-Tsung Kuo,et al.  Design of fast logarithmic converters with high accuracy for digital camera application , 2016, Microsystem Technologies.

[9]  M. Combet,et al.  Computation of the Base Two Logarithm of Binary Numbers , 1965, IEEE Trans. Electron. Comput..

[10]  ERNEST L. HALL,et al.  Generation of Products and Quotients Using Approximate Binary Logarithms for Digital Filtering Applications , 1970, IEEE Transactions on Computers.

[11]  John N. Mitchell,et al.  Computer Multiplication and Division Using Binary Logarithms , 1962, IRE Trans. Electron. Comput..

[12]  Hoi-Jun Yoo,et al.  A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System , 2005, IEEE Journal of Solid-State Circuits.

[13]  Tso-Bing Juang,et al.  Lower-Error Antilogarithmic Converters Using Binary Error Searching Schemes , 2013 .

[14]  Davide De Caro,et al.  Accurate Fixed-Point Logarithmic Converter , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[15]  Hoi-Jun Yoo,et al.  Power and Area-Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems , 2008, IEEE Transactions on Computers.