On the design of a highly testable cell library

In this paper, a new methodology for physical testability analysis is used to derive a new cell library, which can ensure a high coverage of realistic faults, using test patterns derived for Line Stuck-at (LSA) fault detection. The increased testability obtained with this new library, with constrained area overhead, is demonstrated, by means of a test chip implementing one of ISCAS'85 benchmarks (c432) and test circuitry to allow Boundary Scan Test (BST), Built-In Self Test (BIST) and Scan Test of the c432. Simulation results show that, for a 2-metal, CMOS process line dominated by bridging defects, the realistic fault coverage, FCg, can be higher than the gate-level, LSA fault coverage, FC. Interactive cell design is also shown to be rewarding, since increased testability can be obtained. This result is important, since IC design is highly repetitive; hence, a limited effort in cell layout improvement can introduce a significant design improvement.

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