Nanowire-based sublithographic programmable logic arrays

How can Programmable Logic Arrays (PLAs) be built without relying on lithography to pattern their smallest features? In this paper, we detail designs which exploit emerging, bottom-up material synthesis techniques to build PLAs using molecular-scale nanowires. Our new designs accommodate technologies where the only post-fabrication programmable element is a non-restoring diode. We introduce stochastic techniques which allow us to restore the diode logic at the nanoscale so that it can be cascaded and interconnected for general logic evaluation. Under conservative assumptions using 10nm nanowires and 90nm lithographic support, we project yielded logic density around 500,000nm2/or term for a 60 or-term array; a complete 60-term, two-level PLA is roughly the same size as a single 4-LUT logic block in 22nm lithography. Each or term is comparable in area to a 4-transistor hardwired gate at 22nm. Mapping sample datapaths and conventional programmable logic benchmarks, we estimate that each 60-or-term PLA plane will provide equivalent logic to 5--10 4-input LUTs.

[1]  P. Avouris,et al.  Carbon Nanotube Inter- and Intramolecular Logic Gates , 2001 .

[2]  Robert K. Brayton,et al.  Whirlpool PLAs: a regular logic structure and their synthesis , 2002, ICCAD 2002.

[3]  James M. Tour,et al.  Molecular Electronics: Commercial Insights, Chemistry, Devices, Architecture, and Programming , 2003 .

[4]  Charles M. Lieber,et al.  Growth of nanowire superlattice structures for nanoscale photonics and electronics , 2002, Nature.

[5]  André DeHon,et al.  Array-based architecture for FET-based, nanoscale electronics , 2003 .

[6]  Peter M. Kogge,et al.  A Potentially Implementable FPGA for Quantum-Dot Cellular Automata , 2002 .

[7]  Seth Copen Goldstein,et al.  NanoFabrics: spatial computing using molecular electronics , 2001, ISCA 2001.

[8]  S. Tans,et al.  Room-temperature transistor based on a single carbon nanotube , 1998, Nature.

[9]  Alberto L. Sangiovanni-Vincentelli,et al.  Multiple-Valued Minimization for PLA Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  C. Dekker.  Carbon nanotubes as molecular quantum wires , 1999 .

[11]  Lars Samuelson,et al.  One-dimensional steeplechase for electrons realized , 2002 .

[12]  R. Stanley Williams,et al.  Self-assembled growth of epitaxial erbium disilicide nanowires on silicon (001) , 2000 .

[13]  Christopher L. Brown,et al.  Introduction of [2]Catenanes into Langmuir Films and Langmuir-Blodgett Multilayers. A Possible Strategy for Molecular Information Storage Materials , 2000 .

[14]  J. F. Stoddart,et al.  A [2]Catenane-Based Solid State Electronically Reconfigurable Switch , 2000 .

[15]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[16]  André DeHon,et al.  Stochastic assembly of sublithographic nanoscale interfaces , 2003 .

[17]  André DeHon,et al.  DPGA Utilization and Application , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.

[18]  J. F. Stoddart,et al.  Nanoscale molecular-switch crossbar circuits , 2003 .

[19]  S. Chou,et al.  Sub-10 nm imprint lithography and applications , 1997 .

[20]  Charles M. Lieber,et al.  Synthetic Control of the Diameter and Length of Single Crystal Semiconductor Nanowires , 2001 .

[21]  Charles M. Lieber,et al.  Directed assembly of one-dimensional nanostructures into functional networks. , 2001, Science.

[22]  Jason Cong,et al.  Performance-driven mapping for CPLD architectures , 2001, FPGA '01.

[23]  Ken Eguchi,et al.  Construction and use of LB deposition machines for pilot production , 1996 .

[24]  Charles M. Lieber,et al.  A laser ablation method for the synthesis of crystalline semiconductor nanowires , 1998, Science.

[25]  Tiziano Villa,et al.  NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations , 1989, 26th ACM/IEEE Design Automation Conference.

[26]  Charles M. Lieber,et al.  Epitaxial core–shell and core–multishell nanowire heterostructures , 2002, Nature.

[27]  Florian Siegert,et al.  Epitaxial core – shell and core – multishell nanowire heterostructures , 2002 .

[28]  Charles M. Lieber,et al.  High Performance Silicon Nanowire Field Effect Transistors , 2003 .

[29]  André DeHon,et al.  Reconfigurable architectures for general-purpose computing , 1996 .

[30]  Mircea R. Stan,et al.  CMOS/nano co-design for crossbar-based molecular electronic systems , 2003 .

[31]  Huiqun Liu,et al.  Network flow based circuit partitioning for time-multiplexed FPGAs , 1998, ICCAD 1998.

[32]  Charles M. Lieber,et al.  Doping and Electrical Transport in Silicon Nanowires , 2000 .

[33]  Tiziano Villa,et al.  NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations , 1989, 26th ACM/IEEE Design Automation Conference.

[34]  Charles M. Lieber,et al.  Logic Gates and Computation from Assembled Nanowire Building Blocks , 2001, Science.

[35]  A. Ulman,et al.  Ultrathin organic films: From Langmuir-Blodgett to self assembly , 1991 .

[36]  Charles M. Lieber,et al.  Diameter-controlled synthesis of single-crystal silicon nanowires , 2001 .

[37]  P. McEuen,et al.  Single-walled carbon nanotube electronics , 2002 .

[38]  Dongmok Whang,et al.  Large-scale hierarchical organization of nanowire arrays for integrated nanosystems , 2003 .

[39]  Charles M. Lieber,et al.  Functional nanoscale electronic devices assembled using silicon nanowire building blocks. , 2001, Science.

[40]  Gregory S. Snider,et al.  A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology , 1998 .

[41]  Dongmok Whang,et al.  Nanolithography Using Hierarchically Assembled Nanowire Masks , 2003 .

[42]  Charles M. Lieber,et al.  Carbon nanotube-based nonvolatile random access memory for molecular computing , 2000, Science.

[43]  Stoddart,et al.  Electronically configurable molecular-based logic gates , 1999, Science.

[44]  A. El Gamal,et al.  PLA-based FPGA Area Versus Cell C+ Granularity , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.