Reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2nd generation high-k/metal gate transistors

Extensive reliability characterization of a state of the art 32nm strained HK/MG SoC technology with triple transistor architecture is presented here. BTI, HCI and TDDB degradation modes on the Logic and I/O (1.2V, 1.8V and 3.3V tolerant) transistors are studied and excellent reliability is demonstrated. Importance of process optimizations to integrate robust I/O transistors without degrading performance and reliability of Logic transistors emphasized. Finally, Intrinsic and defect reliability monitoring for HVM are addressed.

[1]  R. Chau,et al.  A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.

[2]  S.-J. Choi,et al.  A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[3]  J. Rizk,et al.  RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications , 2010, 2010 International Electron Devices Meeting.

[4]  G. Dewey,et al.  BTI reliability of 45 nm high-K + metal-gate process technology , 2008, 2008 IEEE International Reliability Physics Symposium.

[5]  M. Jones,et al.  Reliability studies on a 45nm low power system-on-chip (SoC) dual gate oxide high-k / metal gate (DG HK+MG) technology , 2010, 2010 IEEE International Reliability Physics Symposium.

[6]  J. Jopling,et al.  Dielectric breakdown in a 45 nm high-k/metal gate process technology , 2008, 2008 IEEE International Reliability Physics Symposium.

[7]  J. Jopling,et al.  High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[8]  Sangwoo Pae,et al.  Frequency and recovery effects in high-κ BTI degradation , 2009, 2009 IEEE International Reliability Physics Symposium.

[9]  Mark Y. Liu,et al.  A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array , 2008, 2008 IEEE International Electron Devices Meeting.

[10]  Mark Y. Liu,et al.  Reliability characterization of 32nm high-K and Metal-Gate logic transistor technology , 2010, 2010 IEEE International Reliability Physics Symposium.

[11]  C. Hu,et al.  A unified gate oxide reliability model , 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

[12]  J. McPherson,et al.  Trends in the ultimate breakdown strength of high dielectric-constant materials , 2003 .

[13]  J. Rizk,et al.  A 32nm low power RF CMOS SOC technology featuring high-k/metal gate , 2010, 2010 Symposium on VLSI Technology.

[14]  C. Auth,et al.  45nm High-k + metal gate strain-enhanced transistors , 2008, 2008 Symposium on VLSI Technology.