A Case Study of Complementary-multiply-with-carry Method on OpenCL FPGA

Field-programmable gate arrays (FPGAs) are becoming a promising heterogeneous computing component for scientific computing. The emerging high-level synthesis tools provide a streamlined design flow to facilitate the use of FPGAs for researchers who have little FPGA development experience. In this paper, we present our implementations of a pseudorandom number generator in a high-level programming language OpenCL, and evaluate its performance and performance per watt on an Arria10-based FPGA platform. We describe the complementary-multiply-with-carry method, and explore its OpenCL implementations under the constraint of hardware resources on the target device. The experimental results show that the raw performance of the implementations on an Intel Arria 10 GX1150 FPGA is 15X lower than that on an Intel Xeon 16-core CPU, but the dynamic power consumption on the FPGA is 60X lower than that on the CPU. For large data size, the performance per watt on the FPGA is 6.7X higher than that on the CPU.

[1]  Donald Ervin Knuth,et al.  The Art of Computer Programming , 1968 .

[2]  Russell Tessier,et al.  FPGA Architecture: Survey and Challenges , 2008, Found. Trends Electron. Des. Autom..

[3]  Yu Ting Chen,et al.  A Survey and Evaluation of FPGA High-Level Synthesis Tools , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Kris Gaj,et al.  An embedded true random number generator for FPGAs , 2004, FPGA '04.

[5]  Abbes Amira,et al.  High Performance FPGA Implementation of the Mersenne Twister , 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

[6]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[7]  Martin Langhammer,et al.  Arria™ 10 device architecture , 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

[8]  Khaled Benkrid,et al.  Mersenne Twister Random Number Generation on FPGA, CPU and GPU , 2009, 2009 NASA/ESA Conference on Adaptive Hardware and Systems.

[9]  Greg Rose.  KISS: A bit too simple , 2017, Cryptography and Communications.

[10]  Chris Rauer,et al.  Accelerating Genomics Research with OpenCL™ and FPGAs , 2017 .

[11]  Jaejin Lee,et al.  Performance characterization of the NAS Parallel Benchmarks in OpenCL , 2011, 2011 IEEE International Symposium on Workload Characterization (IISWC).

[12]  Christophe Guyeux,et al.  FPGA Implementation of F2-Linear Pseudorandom Number Generators based on Zynq MPSoC: A Chaotic Iterations Post Processing Case Study , 2016, SECRYPT.

[13]  Philip Heng Wai Leong,et al.  Compact FPGA-based true and pseudo random number generators , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

[14]  John E. Stone,et al.  OpenCL: A Parallel Programming Standard for Heterogeneous Computing Systems , 2010, Computing in Science & Engineering.

[15]  C. D. Martinez,et al.  An efficient FPGA random number generator using LFSRs and cellular automata , 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).