An Application on Controller to Improve Performance of Multi-Core Shared Memory Based on Network Processing

An application to improve the performance of Multi-Core shared memory based on network processing is described in this paper. In order to get more instructions with address relevancy, the function of chain is applied on the design of SDRAM controller. The application of chain needs to rely on the design of arbitration and command control logic. Firstly, the algorithm of the arbitration is adapted to ensure the function of chain bit. Secondly the command control logic is also optimized to support addressing SDRAM memory efficiently. The verified results show that the efficiency of the SDRAM memory can be improved nearly 47.4% after exploiting more instructions with address relevancy.

[1]  Wei-Fen Lin,et al.  Reducing DRAM latencies with an integrated memory hierarchy design , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[2]  Ramana Rao Kompella,et al.  Analysis of a memory architecture for fast packet buffers , 2001, 2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552).