论文信息 - A quantization noise cancelling fractional-N type ΔΣ frequency synthesizer using SAR-based DAC gain calibration

A quantization noise cancelling fractional-N type ΔΣ frequency synthesizer using SAR-based DAC gain calibration

A high-speed and low-power adaptable period SAR-based DAC gain calibration is presented for DSM quantization noise suppression, which completes within 10μs while dissipating 0.2mW. The proposed calibration scheme is applied to the fractional-N type frequency synthesizer which adopts an 8-bit noise-cancelling DAC. The frequency synthesizer has a range of 48 to 900 MHz, consumes 11mA from 1.2-V supply and occupies 1.5 × 1.4 mm2 in 0.13μm CMOS process. The measurement shows more than 30-dB quantization noise suppression at a 877MHz oscillation frequency which results in the phase noise of -100.7dBc/Hz and -134.5dBc/Hz at 100-kHz and 1.25-MHz offset frequencies respectively.

Sang-Gug Lee | Seungjin Kim | In-Young Lee | Joo-Myoung Kim

[1] Bang-Sup Song,et al. A 1.8GHz Spur-Cancelled Fractional-N Frequency Synthesizer with LMS-Based DAC Gain Calibration , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[2] K.J. Wang,et al. A Wide-Bandwidth 2.4GHz ISM-Band Fractional-N PLL with Adaptive Phase-Noise Cancellation , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3] Bang-Sup Song,et al. A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration , 2006, IEEE Journal of Solid-State Circuits.

[4] M.H. Perrott,et al. A 1-MHZ bandwidth 3.6-GHz 0.18-/spl mu/m CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise , 2006, IEEE Journal of Solid-State Circuits.

[5] Waleed Khalil,et al. A 1 MHz Bandwidth, 6 GHz 0.18 µm CMOS Type-I ΔΣ Fractional-NSynthesizer for WiMAX Applications , 2009, IEEE J. Solid State Circuits.

[6] Ian Galton,et al. A Wide-Bandwidth 2.4 GHz ISM Band Fractional-$N$ PLL With Adaptive Phase Noise Cancellation , 2007, IEEE Journal of Solid-State Circuits.