Leading-zero anticipatory logic for high-speed floating point addition

This paper describes new Leading-Zero Anticipatory (LZA) Logic for high-speed floating-point addition (FADD). This method carries out the pre-decoding for the normalization concurrently with the addition for significand. Besides, it performs the shift operation in parallel with the rounding operation. The proposed logic consists of the simple circuit with 1.8% penalty in transistor count. The FADD core using the proposed logic operates at 160 MHz, where the core has been fabricated with 0.5 /spl mu/m CMOS technology with triple metal interconnections.