A Difference Reference Voltage Buffer for ΔΣ-Converters
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An open loop architecture for a reference voltage buffer in ΔΣ-converters is presented to achieve fast-settling, since the settling time of the references plays an important role in the global performance of sampled data converters. This design has been tested on a 2-1 ΔΣ-converter with an on-chip bandgap reference increasing the input related dynamic range up to 93.4 dB for a bandwidth of 99 kHz.
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