Chip Scale Package Technology
暂无分享,去创建一个
[1] Satoshi Tanigawa,et al. The resin molded chip size package (MCSP) , 1995, Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'.
[2] R. Ghaffarian. Chip Scale Package and Assembly Joint Reliability , 1999 .
[3] Miguel Jimarez,et al. MCM-L Substrates for a 300 MHz Workstation , 1995 .
[4] T. Chou,et al. A low‐cost chip size package – NuCSP , 1998 .
[5] Happy T. Holden. Comparing Costs for Various Pwb Build-Up Technologies , 1996 .
[6] Young-Gon Kim,et al. Ultra-thin and crack-free bottom leaded plastic (BLP) package design , 1995, 1995 Proceedings. 45th Electronic Components and Technology Conference.
[7] J.-P. Clech,et al. RELIABILITY PREDICTION MODELING OF AREA ARRAY CSPS , 1997 .
[8] Shinji Baba,et al. Molded chip scale package for high pin count , 1996 .
[9] R. Ghaffarian. Chip Scale Package Joint Integrity of CSP under Isothermal Aging , 1998 .
[10] M. Hou. Wafer level packaging for CSPs : Assembly and packaging , 1998 .
[11] Wei Lin,et al. TBGA reliability in telecom environment , 2000 .
[12] Yutaka Tsukada,et al. Surface laminar circuit packaging , 1992, 1992 Proceedings 42nd Electronic Components & Technology Conference.
[13] Osamu Yoshioka,et al. CSP with LOC technology , 1997 .
[14] P. Lall,et al. Reliability characterization of the SLICC package , 1996, 1996 Proceedings 46th Electronic Components and Technology Conference.
[16] J. Partridge,et al. TAKING THE CSP PLUNGE , 1999 .
[17] Yoshinobu Kunitomo,et al. CSP (Chip Size Package) , 1995 .
[18] John H. Lau,et al. Chip scale package (CSP) : design, materials, processes, reliability, and applications , 1999 .
[19] J. P. Partridge,et al. Influence of process variables on the reliability of microBGA/sup TM/ package assemblies , 1998, 1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206).
[20] S. C. Hung,et al. Board level reliability of Chip scale packages , 1999 .
[21] P. Thompson,et al. Chip-scale packaging , 1997 .
[22] J. H. Lau,et al. Solder joint reliability of a low cost chip size package—NuCSP , 1998 .
[23] C.L. Lassen,et al. The via squeeze , 1999, IEEE Spectrum.
[24] Yoshihiro Tomura,et al. A Stud-bump-bonding Technique For High Density Multi-chip-module , 1993, Proceedings of Japan International Electronic Manufacturing Technology Symposium.
[25] A. Mawer,et al. Reliability assessment of a thin (flex) BGA using a polyimide tape substrate , 1999, Twenty Fourth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.99CH36330).
[26] Myung K. Kim,et al. Bottom leaded plastic (BLP) package: a new design with enhanced solder joint reliability , 1996, 1996 Proceedings 46th Electronic Components and Technology Conference.
[27] R. Ghaffarian. CSPs Assembly Reliability , 1997 .
[28] Rajen Chanchani,et al. mini Ball Grid Array (mBGA) assembly on MCM-L boards , 1997 .
[29] K. Puttlitz. Preparation, structure, and fracture modes of Pb-Sn and Pb-In terminated flip chips attached to gold-capped microsockets , 1990 .
[30] R.N. Master,et al. Ceramic mini-ball grid array package for high speed device , 1995, 1995 Proceedings. 45th Electronic Components and Technology Conference.
[31] J. Lau. Ball Grid Array Technology , 1994 .
[32] Yasuhisa Yamaji,et al. Board level reliability of CSP , 1998, 1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206).
[33] J. Lau,et al. Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies , 1996 .
[34] Pradeep Lall,et al. Assembly-level reliability of flex-substrate BGA, elastomer-on-flex packages and 0.5 mm pitch partial array packages , 2000 .
[35] L. Nguyen,et al. Wafer level Chip Scale packaging : Solder joint reliability , 1998 .
[36] T. Saitoh,et al. Development of chip scale packages (CSP) for center pad devices , 1997, 1997 Proceedings 47th Electronic Components and Technology Conference.
[37] Yasuhisa Yamaji,et al. Development of highly reliable CSP , 1997, 1997 Proceedings 47th Electronic Components and Technology Conference.
[38] Aaron DerMarderosian,et al. The Effects of Entrapped Bubbles in Solder Used for the Attachment of Leadless Ceramic Chip Carriers , 1983, 21st International Reliability Physics Symposium.
[39] John H. Lau,et al. A low‐cost solder‐bumped chip scale package ‐NuCSP , 1998 .
[40] H. M. Clearfield,et al. Development of Wafer Level Packaging for Integrated Passive Devices , 1999 .
[41] T. C. Chung,et al. Area array packaging technologies for high-performance computer workstations and multiprocessors , 1996, 1996 Proceedings 46th Electronic Components and Technology Conference.
[42] V. Sarihan,et al. JACS-Pak/sup TM/ flip-chip chip scale package development and characterization , 1998, 1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206).
[43] T. Tessier,et al. a Comparative Analysis of High Density Pwb Technologies , 1996 .
[44] James Wilson Rose,et al. Development of GE's plastic thin-zero outline package (TZOP) technology , 1995, 1995 Proceedings. 45th Electronic Components and Technology Conference.
[45] Hiroshi Iwasaki. CSTP (Chip Scale Thin Package) , 1995 .
[46] R. A. Fillion,et al. Chip scale packaging using chip-on-flex technology , 1997, 1997 Proceedings 47th Electronic Components and Technology Conference.
[47] T. Tachikawa,et al. Chip scale package (CSP) "a lightly dressed LSI chip" , 1994, Proceedings of 16th IEEE/CPMT International Electronic Manufacturing Technology Symposium.