HIFSuite: Tools for HDL Code Conversion and Manipulation

HIFSuite ia a set of tools and application programming interfaces (APIs) that provide support for modeling and verification of HW/SW systems. The core of HIFSuite is the HDL Intermediate Format (HIF) language upon which a set of front-end and back-end tools have been developed to allow the conversion of HDL code into HIF code and vice versa. HIFSuite allows designers to manipulate and integrate heterogeneous components implemented by using different hardware description languages (HDLs). Moreover, HIFSuite includes tools, which rely on HIF APIs, for manipulating HIF descriptions in order to support code abstraction/refinement and postrefinement verification.

[1]  Stuart Swan,et al.  A tutorial introduction on the new SystemC verification standard , 2003 .

[2]  F. Fummi,et al.  Improving High-Level and Gate-Level Testing with FATE: a Functional ATPG Traversing Unstabilized EFSMs , 2007 .

[3]  Pedro J. Gil,et al.  Comparison and application of different VHDL-based fault injection techniques , 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[4]  F. Fummi,et al.  On the Reuse of VHDL Modules into SystemC Design , 2001 .

[5]  Franco Fummi,et al.  Logic-level mapping of high-level faults , 2005, Integr..

[6]  Rached Tourki,et al.  Communication Architecture Synthesis for Multi-bus SoC , 2006 .

[7]  David J. Greaves,et al.  Using RTL-to-C++ translation for large soc concurrent engineering: a case study , 2003 .

[8]  Franco Fummi,et al.  FATE: a Functional ATPG to Traverse Unstabilized EFSMs , 2006, Eleventh IEEE European Test Symposium (ETS'06).

[9]  Yvon Savaria,et al.  The role of model-level transactors and UML in functional prototyping of systems-on-chip: a software-radio application , 2005, Design, Automation and Test in Europe.

[10]  Mark Glasser,et al.  The Transaction-Based Verification Methodology , 2000 .

[11]  Marco Pistore,et al.  NuSMV 2: An OpenSource Tool for Symbolic Model Checking , 2002, CAV.

[12]  C. Cote,et al.  Automated SystemC to VHDL translation in hardware/software codesign , 2002, 9th International Conference on Electronics, Circuits and Systems.

[13]  Franco Fummi,et al.  A Mutation Model for the SystemC TLM 2.0 Communication Interfaces , 2008, 2008 Design, Automation and Test in Europe.

[14]  J. Arlat,et al.  Integration and Comparison of Three Physical Fault Injection Techniques , 1995 .

[15]  Franco Fummi,et al.  A methodology for abstracting RTL designs into TL descriptions , 2006, Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings..

[16]  Massimo Bombana,et al.  SystemC-VHDL co-simulation and synthesis in the HW domain , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[17]  Roberto Passerone,et al.  Specification, Synthesis, and Simulation of Transactor Processes , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Teruo Higashino,et al.  Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization , 2000, Proceedings 37th Design Automation Conference.

[19]  Franco Fummi,et al.  LAERTE++: an Object Oriented High-level TPG for SystemC Designs , 2003, FDL.

[20]  R. D. Blanton,et al.  Diagnostic Test Generation for Arbitrary Faults , 2006, 2006 IEEE International Test Conference.

[21]  A. Sudnitson,et al.  Register transfer low power design based on controller decomposition , 2004, 2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716).

[22]  Kshitiz Jain,et al.  Verification of transaction-level SystemC models using RTL testbenches , 2003, First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings..

[23]  Abdelaziz Guerrouat,et al.  A component-based specification approach for embedded systems using FDTs , 2005, SAVCBS '05.

[24]  Imed Moussa,et al.  An integrated design and verification methodology for reconfigurable multimedia systems , 2005, Design, Automation and Test in Europe.

[25]  Franco Fummi,et al.  Properties Incompleteness Evaluation by Functional Verification , 2007, IEEE Transactions on Computers.

[26]  Kwang-Ting Cheng,et al.  Automatic generation of functional vectors using the extended finite state machine model , 1996, TODE.

[27]  Joao Marques-Silva,et al.  Towards Equivalence Checking Between TLM and RTL Models , 2007, 2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007).

[28]  Raphael R. Some,et al.  A software-implemented fault injection methodology for design and validation of system fault tolerance , 2001, 2001 International Conference on Dependable Systems and Networks.

[29]  Johan Karlsson,et al.  Fault injection into VHDL models: the MEFISTO tool , 1994 .