A Region-Based Through-Silicon via Repair Method for Clustered Faults
暂无分享,去创建一个
[1] Israel Koren,et al. Defect tolerance in VLSI circuits: techniques and yield analysis , 1998, Proc. IEEE.
[2] TingTing Hwang,et al. TSV Redundancy: Architecture and Design Issues in 3-D IC , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[3] Sungho Kang,et al. Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[4] Yiyu Shi,et al. Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[5] Mehdi Baradaran Tahoori. Defects, yield, and design in sublithographic nano-electronics , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).
[6] Chenchen Deng,et al. A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures , 2015, The 20th Asia and South Pacific Design Automation Conference.
[7] Huaguo Liang,et al. Pulse shrinkage based pre-bond through silicon vias test in 3D IC , 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).
[8] Qiang Xu,et al. On Effective Through-Silicon Via Repair for 3-D-Stacked ICs , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Young-Hyun Jun,et al. 8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology , 2009, IEEE Journal of Solid-State Circuits.
[10] Qiang Xu,et al. On effective TSV repair for 3D-stacked ICs , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[11] Luca Benini,et al. A low-overhead fault tolerance scheme for TSV-based 3D network on chip links , 2008, ICCAD 2008.
[12] Sungho Kang,et al. FRESH: A New Test Result Extraction Scheme for Fast TSV Tests , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] Jun Zhou,et al. BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.