FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

The mathematical model for designing a complex digital system is a finite state machine (FSM). Applications such as digital signal processing (DSP) and built-in self-test (BIST) require specific operations to be performed only in the particular instances. Hence, the optimal synthesis of such systems requires a reconfigurable FSM. The objective of this paper is to create a framework for a reconfigurable FSM with input multiplexing and state-based input selection (Reconfigurable FSMIM-S) architecture. The Reconfigurable FSMIM-S architecture is constructed by combining the conventional FSMIM-S architecture and an optimized multiplexer bank (which defines the mode of operation). For this, the descriptions of a set of FSMs are taken for a particular application. The problem of obtaining the required optimized multiplexer bank is transformed into a weighted bipartite graph matching problem where the objective is to iteratively match the description of FSMs in the set with minimal cost. As a solution, an iterative greedy heuristic based Hungarian algorithm is proposed. The experimental results from MCNC FSM benchmarks demonstrate a significant speed improvement by 30.43% as compared with variation-based reconfigurable multiplexer bank (VRMUX) and by 9.14% in comparison with combination-based reconfigurable multiplexer bank (CRMUX) during field programmable gate array (FPGA) implementation.

[1]  Ignacio Garcia-Vargas,et al.  Finite State Machines With Input Multiplexing: A Performance Study , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Rakesh Nagi,et al.  GPU-accelerated Hungarian algorithms for the Linear Assignment Problem , 2016, Parallel Comput..

[3]  Valery Sklyarov,et al.  Synthesis of parallel hierarchical finite state machines , 2013, 2013 21st Iranian Conference on Electrical Engineering (ICEE).

[4]  Jayanta Dutta,et al.  A note on Hungarian method for solving assignment problem , 2015 .

[5]  Alexander Barkalov,et al.  Designing LUT-based mealy FSM with transformation of collections of output functions , 2016 .

[6]  Ignacio Garcia-Vargas,et al.  ROM-based FSM implementation using input multiplexing in FPGA devices , 2004 .

[7]  Dong Yang,et al.  Design and application of multi-stage reconfigurable signal processing flow on FPGA , 2015, Comput. Electr. Eng..

[8]  Valery Salauyou.  Synthesis of High-Speed Finite State Machines in FPGAs by State Splitting , 2016, CISIM.

[9]  Erwin Pesch,et al.  Minimizing maximum weight of subsets of a maximum matching in a bipartite graph , 2015, Discret. Appl. Math..

[11]  Eduardo L. Pasiliao,et al.  A simple greedy heuristic for linear assignment interdiction , 2017, Ann. Oper. Res..

[12]  Ignacio Garcia-Vargas,et al.  High-Speed and Area-Efficient Reconfigurable Multiplexer Bank for RAM-Based Finite State Machine Implementations , 2015, J. Circuits Syst. Comput..

[13]  Ajit Singh,et al.  An evolutionary heuristic algorithm for the assignment problem , 2014 .

[14]  Aiman H. El-Maleh,et al.  A probabilistic pairwise swap search state assignment algorithm for sequential circuit optimization , 2017, Integr..

[15]  Adam Klimowicz,et al.  Minimization Method of Finite State Machines for Low Power Design , 2015, 2015 Euromicro Conference on Digital System Design.

[16]  Aiman H. El-Maleh,et al.  Majority-based evolution state assignment algorithm for area and power optimisation of sequential circuits , 2016, IET Comput. Digit. Tech..

[17]  Inmaculada Pardines,et al.  DSPONE48: A methodology for automatically synthesize HDL focus on the reuse of DSP slices , 2017, J. Parallel Distributed Comput..

[18]  Michał Doligalski,et al.  Design of Reconfigurable Logic Controllers , 2015 .

[19]  Shubham Gupta,et al.  Realization of sequential reversible circuit from finite state machine , 2014, 2014 International Computer Science and Engineering Conference (ICSEC).

[20]  Sambhu Nath Pradhan,et al.  Low power and high testable Finite State Machine synthesis , 2015, 2015 International Conference and Workshop on Computing and Communication (IEMCON).

[21]  Kevin Barraclough,et al.  I and i , 2001, BMJ : British Medical Journal.

[22]  R. Brindha,et al.  An enhanced architecture for high performance BIST TPG , 2015, 2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS).

[23]  Jan Haase,et al.  TR-FSM: Transition-Based reconfigurable finite state machine , 2011, TRETS.

[24]  Tiziano Villa,et al.  NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations , 1989, 26th ACM/IEEE Design Automation Conference.