Dual band CMOS LNA design with current reuse topology

A new architecture of dual band receiver was introduced; it is able to make simultaneous operations at two different frequency bands. This architecture uses a new dual band low noise amplifier (LNA). A novel high gain and low noise amplifier topology is proposed. This paper presents a general methodology to design a LNA with current reuse topology for the two standards GSM and UMTS at 947.5MHz and 2.14GHz frequencies respectively, A fully integrated dual band LNA was designed using 0.35mum CMOS process. At 947.5MHz, the LNA exhibits a noise figure of 2.3dB, a voltage gain of 28dB, a CP1 of -12dBm. However, the LNA at 2.14GHz features a noise figure of 2.71dB, a voltage gain of 17dB and a CP1 of -4.5dBm. The power consumption is 37.5mW under a power supply voltage of 2.5V

[1]  T.H. Lee,et al.  A physical model for planar spiral inductors on silicon , 1996, International Electron Devices Meeting. Technical Digest.

[2]  Ali M. Niknejad,et al.  Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs , 1998, IEEE J. Solid State Circuits.

[3]  A. Karanicolas.  A 2.7 V 900 MHz CMOS LNA and mixer , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[4]  Pietro Andreani,et al.  Noise optimization of an inductively degenerated CMOS low noise amplifier , 2001 .

[5]  Choong-Yul Cha,et al.  A low power, high gain LNA topology , 2000, ICMMT 2000. 2000 2nd International Conference on Microwave and Millimeter Wave Technology Proceedings (Cat. No.00EX364).