Communication-aware task scheduling for multi-core architectures with segmented buses

As the number of cores on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance, and energy consumption of the overall system. This paper presents a mesh-like connected multi-core architecture with segmented buses to meet the requirements of high performance and low energy consumption. Based on the proposed architecture, a communication-aware greedy task scheduling is designed to minimize the communication energy consumption among cores while maintaining the same performance as other scheduling algorithms. We evaluate the algorithm performance through a series of experiments with Gaussian Elimination, and the experimental results confirm the effectiveness of the algorithm.

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