A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM

The spin-transfer torque magnetic random access memory (STT-MRAM) is an emerging memory technology with several distinctive advantages such as nonvolatility, high density, scalability, and almost unlimited endurance. It is, therefore, seen as a promising candidate to replace conventional on-chip memory technologies. However, as the technology scales, yield loss due to extreme parametric variations is becoming increasingly important for STT-MRAM because of its higher sensitivity to process variation as compared to CMOS memories. In addition, the parametric variations in STT-MRAM exacerbate its stochastic switching behavior, leading to both test time fails and reliability failures in the field. Since an STT-MRAM memory array consists of both CMOS and magnetic components, the system-level failures in STT-MRAM depend on variations in both these components. In this paper, we model the system-level parametric failures of STT-MRAM considering the spatial correlation among bit cells as well as the impact of peripheral components. The proposed approach provides realistic fault distribution maps and equips the designer to investigate the efficacy of different combinations of defect tolerance techniques for an effective design-for-yield exploration. The results show that the fault distribution and yield depend on the correlation coefficient and the temperature, which, in turn, determine the correct choice of defect tolerance scheme to be adopted to mitigate them to improve the yield.

[1]  M. Hosomi,et al.  A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[2]  Mehdi Baradaran Tahoori,et al.  Improving reliability, performance, and energy efficiency of STT-MRAM with dynamic write latency , 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

[3]  B. Dieny,et al.  A compact model of precessional spin-transfer switching for MTJ with a perpendicular polarizer , 2012, 2012 28th International Conference on Microelectronics Proceedings.

[4]  Mehdi Baradaran Tahoori,et al.  A cross-layer adaptive approach for performance and power optimization in STT-MRAM , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[5]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[6]  Mehdi Baradaran Tahoori,et al.  Read disturb fault detection in STT-MRAM , 2014, 2014 International Test Conference.

[7]  J. Torrellas,et al.  VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects , 2008, IEEE Transactions on Semiconductor Manufacturing.

[8]  Yiran Chen,et al.  An overview of non-volatile memory technology and the implication for tools and architectures , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[9]  Kaushik Roy,et al.  Modeling of failure probability and statistical design of Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) array for yield enhancement , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[10]  Xueti Tang,et al.  Spin-transfer torque magnetic random access memory (STT-MRAM) , 2013, JETC.

[11]  Youguang Zhang,et al.  Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology , 2015, IEEE Transactions on Electron Devices.

[12]  Mircea R. Stan,et al.  Relaxing non-volatility for fast and energy-efficient STT-RAM caches , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[13]  Mehdi B. Tahoori,et al.  Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  M. D. Giles,et al.  Process Technology Variation , 2011, IEEE Transactions on Electron Devices.

[15]  Mircea R. Stan,et al.  The Promise of Nanomagnetics and Spintronics for Future Logic and Universal Memory , 2010, Proceedings of the IEEE.

[16]  Arijit Raychowdhury,et al.  Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays , 2016, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[17]  Lirida Alves de Barros Naviner,et al.  Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy , 2016, Materials.

[18]  Cheng-Wen Wu,et al.  An integrated ECC and redundancy repair scheme for memory reliability enhancement , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[19]  Bruce Jacob,et al.  Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[20]  Mehdi B. Tahoori,et al.  VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Yiran Chen,et al.  Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  A. Fert,et al.  Current-induced magnetization switching in atom-thick tungsten engineered perpendicular magnetic tunnel junctions with large tunnel magnetoresistance , 2017, Nature Communications.

[23]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[24]  Andrew D Kent,et al.  A new spin on magnetic memories. , 2015, Nature nanotechnology.

[25]  Mehdi Baradaran Tahoori,et al.  Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM , 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

[26]  Mehdi Baradaran Tahoori,et al.  Opportunistic write for fast and reliable STT-MRAM , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[27]  Avik W. Ghosh,et al.  A Quasi-Analytical Model for Energy-Delay-Reliability Tradeoff Studies During Write Operations in a Perpendicular STT-RAM Cell , 2012, IEEE Transactions on Electron Devices.

[28]  Cong Xu,et al.  NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[29]  Min Chen,et al.  Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[30]  S. Thompson,et al.  Moore's law: the future of Si microelectronics , 2006 .

[31]  Youguang Zhang,et al.  Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM , 2015, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[32]  Takayuki Kawahara,et al.  Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing , 2011, IEEE Design & Test of Computers.

[33]  Said Hamdioui,et al.  Testing static and dynamic faults in random access memories , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[34]  Mahmut T. Kandemir,et al.  Leakage Current: Moore's Law Meets Static Power , 2003, Computer.

[35]  Massimo Alioto,et al.  Dynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMs , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[36]  Mehdi B. Tahoori,et al.  Improving Write Performance for STT-MRAM , 2016, IEEE Transactions on Magnetics.

[37]  Swaroop Ghosh,et al.  Impact of process-variations in STTRAM and adaptive boosting for robustness , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[38]  Mehdi Baradaran Tahoori,et al.  Parametric failure modeling and yield analysis for STT-MRAM , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).