Implementation of PCI Express bus communication for FPGA-based data acquisition system

This paper presents a PCI Express based system dedicated for communication with FPGA in data acquisition systems. The system consisted of FPGA IP core containing PCIE endpoint tightly coupled with with the user core (further denoted as “USR core”) and the DDR3 memory controller, together with Linux device driver. The Linux OS was running on top of typical x86-64 system.