A Review on Compact Modeling of Multiple-Gate MOSFETs
暂无分享,去创建一个
Yuan Taur | Bo Yu | Yu Yuan | Jooyoung Song | Y. Taur | Bo Yu | Yu Yuan | Jooyoung Song
[1] Luca Selmi,et al. Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.
[2] B. Iñíguez,et al. Compact model for short channel symmetric doped double-gate MOSFETs , 2008 .
[3] Y. Taur,et al. A Unified Analytic Drain–Current Model for Multiple-Gate MOSFETs , 2008, IEEE Transactions on Electron Devices.
[4] Alfonso Limon,et al. A compact model for the I-V characteristics of an undoped double-gate MOSFET , 2008, Math. Comput. Simul..
[5] Quasi 3-D Velocity Saturation Model for Multiple-Gate MOSFETs , 2007, IEEE Transactions on Electron Devices.
[6] Christian Enz,et al. A Design Oriented Charge-based Current Model for Symmetric DG MOSFET and its Correlation with the EKV Formalism , 2005 .
[7] Yuan Taur,et al. Explicit Continuous Models for Double-Gate and Surrounding-Gate MOSFETs , 2007, IEEE Transactions on Electron Devices.
[8] D. Jimenez,et al. Explicit Analytical Charge and Capacitance Models of Undoped Double-Gate MOSFETs , 2007, IEEE Transactions on Electron Devices.
[9] G. Gildenblat,et al. PSP-based compact FinFET model describing dc and RF measurements , 2006, 2006 International Electron Devices Meeting.
[10] Yuan Taur,et al. A 2-D analytical solution for SCEs in DG MOSFETs , 2004 .
[11] B. Iñíguez,et al. Continuous analytic I-V model for surrounding-gate MOSFETs , 2004, IEEE Electron Device Letters.
[12] Bastien Giraud,et al. A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology , 2008, 2008 IEEE International Symposium on Circuits and Systems.
[13] Christophe Lallement,et al. Explicit modelling of the double-gate MOSFET with VHDL-AMS , 2006 .
[14] J. Brews. A charge-sheet model of the MOSFET , 1978 .
[15] C. Hu,et al. BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design , 2007, 2007 IEEE Symposium on VLSI Technology.
[16] Adelmo Ortiz-Conde,et al. Unification of asymmetric DG, symmetric DG and bulk undoped-body MOSFET drain current , 2006 .
[17] G. Gildenblat,et al. Analytical approximation for the MOSFET surface potential , 2001 .
[18] Y. Tsividis. Operation and modeling of the MOS transistor , 1987 .
[19] Yuan Taur,et al. Compact modeling of multiple-gate MOSFETs , 2008 .
[20] Yuan Taur,et al. An analytic model for threshold voltage shift due to quantum confinement in surrounding gate MOSFETs with anisotropic effective mass , 2009 .
[21] Ali M. Niknejad,et al. A versatile multi-gate MOSFET compact model: BSIM-MG , 2007 .
[22] Christophe Lallement,et al. Explicit compact model for symmetric double-gate MOSFETs including solutions for small-geometry effects , 2008 .
[23] 裕幸 飯田,et al. International Technology Roadmap for Semiconductors 2003の要求清浄度について - シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について - , 2004 .
[24] Francois Krummenacher,et al. Explicit modelling of the double-gate MOSFET with VHDL-AMS: Research Articles , 2006 .
[25] Y. Taur,et al. A continuous, analytic drain-current model for DG MOSFETs , 2004 .
[26] J.J. Liou,et al. A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs , 2007, IEEE Transactions on Electron Devices.
[27] H. A. Hamid,et al. Explicit continuous model for long-channel undoped surrounding gate MOSFETs , 2005, IEEE Transactions on Electron Devices.
[28] Jean-Pierre Colinge,et al. Quantum-mechanical effects in nanometer scale MuGFETs , 2008 .
[29] Y. Taur. An analytical solution to a double-gate MOSFET with undoped body , 2000 .
[30] C. C. McAndrew,et al. An improved MOSFET model for circuit simulation , 1998 .
[31] D. Flandre,et al. A 3-D Analytical Physically Based Model for the Subthreshold Swing in Undoped Trigate FinFETs , 2007, IEEE Transactions on Electron Devices.
[32] Yuan Taur,et al. An analytic potential model for symmetric and asymmetric DG MOSFETs , 2006, IEEE Transactions on Electron Devices.
[33] Chung-Hsun Lin,et al. A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation , 2007, 2007 IEEE International Electron Devices Meeting.
[34] G. Gildenblat,et al. PSP-based scalable compact FinFET model , 2007 .
[35] G.D.J. Smit,et al. Symmetric linearization method for double-gate and surrounding-gate MOSFET models , 2009 .
[36] Joao Antonio Martino,et al. Threshold voltages of SOI MuGFETs , 2008 .
[37] Chenming Hu,et al. Modeling Advanced FET Technology in a Compact Model , 2006, IEEE Transactions on Electron Devices.
[38] D. Munteanu,et al. Quantum short-channel compact modeling of drain-current in double-gate MOSFET , 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..
[39] Jean-Pierre Colinge,et al. Multiple-gate SOI MOSFETs , 2004 .
[40] Yuan Taur,et al. Experimental Hardware Calibrated Compact Models for 50nm n-channel FinFETs , 2007, 2007 IEEE International SOI Conference.
[41] Antonio Cerdeira,et al. Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETs , 2008 .
[42] Yuan Taur,et al. A unified charge model for symmetric double-gate and surrounding-gate MOSFETs , 2008 .
[43] R.W. Dutton,et al. A charge-oriented model for MOS transistor capacitances , 1978, IEEE Journal of Solid-State Circuits.
[44] Chenming Hu,et al. A Compact Quantum-Mechanical Model for Double-Gate MOSFET , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.
[45] Benjamin Iniguez,et al. Compact charge and capacitance modeling of undoped ultra-thin body (UTB) SOI MOSFETs , 2008 .
[46] Yuan Taur,et al. Analytic Charge Model for Surrounding-Gate MOSFETs , 2007, IEEE Transactions on Electron Devices.