Statistical modeling and analysis of wafer test fail counts
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This paper presents a yield analysis technique based on test fail counts, as these are the most comprehensive and fundamental yield data available. Obviously, this requires the analysis of large volumes of data. Using powerful statistical techniques, such as Principal Component Analysis (PCA) and Multiple Linear Regression (MLR), efficient data reduction is achieved. A basic concept for the modeling of both defect related and parametric fails is presented. Based on a real life examples, means, variances, and covariances of test fail counts are analyzed. As covariance turns out to play a significant role, it is further analyzed using PCA to work out major independent sources of variation. MLR is then applied to partition total yield loss, resulting in the complete representation of actual yield data by just a few relevant patterns. Identification of physical root causes is consequently greatly simplified and accelerated, leading to fast problem solving and yield improvement.
[1] Ping Yang,et al. Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits , 1983, 1983 International Electron Devices Meeting.
[2] C. Stapper. The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions , 1985 .
[3] Wojciech Maly,et al. Yield loss forecasting in the early phases of the VLSI design process , 1996, Proceedings of Custom Integrated Circuits Conference.