Assessing the diagnostic power of test pattern sets

Abstract The increasing power of the available fault simulators makes it possible to satisfy new requirements such as statistics and other data about both the testability and the diagnosability of circuits. Commercial fault simulators are often unable to provide this kind of information and, even when they provide some diagnostic facilities, they are highly inefficient in implementing them. This paper introduces a general framework to analyze the problem and presents an ad hoc strategy based on efficient techniques for both simulation and fault dropping. A prototype simulator, able to produce full diagnostic information with acceptable CPU time and memory requirements, is described.

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