Mixed-Criticality Scheduling upon Varying-Speed Processors

A varying-speed processor is characterized by two execution speeds: a normal speed and a degraded speed. Under normal circumstances it will execute at its normal speed, conditions during run-time may cause it to execute more slowly (but no slower than at its degraded speed). The problem of executing an integrated workload, consisting of some more important components and some less important ones, upon such a varying-speed processor is considered. It is desired that all components execute correctly under normal circumstances, whereas the more important components should execute correctly (although the less important components need not) if the processor runs at any speed no slower than its specified degraded speed.

[1]  Sanjoy K. Baruah,et al.  Optimal utilization bounds for the fixed-priority scheduling of periodic task systems on identical multiprocessors , 2004, IEEE Transactions on Computers.

[2]  Sanjoy K. Baruah,et al.  Mixed-criticality scheduling on multiprocessors , 2013, Real-Time Systems.

[3]  Jane W.-S. Liu.  Real-Time Systems , 2000, Encyclopedia of Algorithms.

[4]  S. Vestal.  Preemptive Scheduling of Multi-criticality Systems with Varying Degrees of Execution Time Assurance , 2007, RTSS 2007.

[5]  L. Khachiyan.  Polynomial algorithms in linear programming , 1980 .

[6]  L. G. H. Cijan.  A polynomial algorithm in linear programming , 1979 .

[7]  Lui Sha,et al.  Memory Access Control in Multiprocessor for Real-Time Systems with Mixed Criticality , 2012, 2012 24th Euromicro Conference on Real-Time Systems.

[8]  Asaf Shapira,et al.  Approximate Hypergraph Partitioning and Applications , 2007, 48th Annual IEEE Symposium on Foundations of Computer Science (FOCS'07).

[9]  Narendra Karmarkar,et al.  A new polynomial-time algorithm for linear programming , 1984, Comb..

[10]  Shui Lam,et al.  A Level Algorithm for Preemptive Scheduling , 1977, J. ACM.

[11]  Alan Burns,et al.  Response-Time Analysis for Mixed Criticality Systems , 2011, 2011 IEEE 32nd Real-Time Systems Symposium.

[12]  Kirk Pruhs,et al.  Non-Preemptive Min-Sum Scheduling with Resource Augmentation , 2007, 48th Annual IEEE Symposium on Foundations of Computer Science (FOCS'07).

[13]  Sanjoy K. Baruah,et al.  Sustainable Multiprocessor Scheduling of Sporadic Task Systems , 2009, 2009 21st Euromicro Conference on Real-Time Systems.

[14]  Jakob Engblom,et al.  The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.

[15]  Robert I. Davis,et al.  Mixed Criticality Systems - A Review , 2015 .

[16]  Risat Mahmud Pathan,et al.  Schedulability Analysis of Mixed-Criticality Systems on Multiprocessors , 2012, 2012 24th Euromicro Conference on Real-Time Systems.

[17]  Chung Laung Liu,et al.  Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment , 1989, JACM.

[18]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[19]  David Blaauw,et al.  A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation , 2011, IEEE Journal of Solid-State Circuits.

[20]  Jan Karel Lenstra,et al.  Complexity of machine scheduling problems , 1975 .

[21]  Aloysius Ka-Lau Mok,et al.  Fundamental design problems of distributed systems for the hard-real-time environment , 1983 .

[22]  Sanjoy Baruah,et al.  Mixed-criticality scheduling upon unreliable processors , 2013 .

[23]  Nuno Pereira,et al.  Static-Priority Scheduling over Wireless Networks with Multiple Broadcast Domains , 2007, RTSS 2007.

[24]  David Blaauw,et al.  A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[25]  Sanjoy K. Baruah,et al.  The Preemptive Uniprocessor Scheduling of Mixed-Criticality Implicit-Deadline Sporadic Task Systems , 2012, 2012 24th Euromicro Conference on Real-Time Systems.