High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness

Power optimization has become an important issue for high performance designs. One way to achieve low-power and high performance circuits is to use dual-threshold voltages. High threshold transistors can be used in non-critical paths to reduce the leakage power, while lower threshold voltage is used for transistors in critical path(s) to achieve high performance. This paper proposes two low power and high performance CMOS design techniques-multiple channel length (M/sub L/CMOS) and multiple oxide thickness (M/sub ox/CMOS), based on dual V/sub th/, design technique. A comprehensive algorithm for selecting and assigning optimal transistor threshold voltage, channel length and oxide thickness is given. The simulation results on ISCAS benchmark circuits show that the total power consumption can be reduced by 21% for M/sub L/CMOS at low activity. Total power savings for M/sub ox/CMOS at low and high switching activities are about 42% and 24%, respectively.

[1]  Siegfried Selberherr,et al.  MINIMOS—A two-dimensional MOS transistor analyzer , 1980 .

[2]  R.Y. Chang,et al.  A highly manufacturable 0.25 /spl mu/m multiple-Vt dual gate oxide CMOS process for logic/embedded IC foundry technology , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[3]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[4]  Kaushik Roy,et al.  Estimation of sequential circuit activity considering spatial and temporal correlations , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[5]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[6]  H. Grubin.  The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.

[7]  Ping Yang,et al.  A Monte Carlo approach for power estimation , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[8]  James D. Meindl,et al.  Low power microelectronics: retrospect and prospect , 1995, Proc. IEEE.

[9]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[10]  Mark C. Johnson,et al.  Design and optimization of dual-threshold circuits for low-voltage low-power applications , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Mark C. Johnson,et al.  Models and algorithms for bounds on leakage in CMOS circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Rajendran Panda,et al.  Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing , 1999, DAC '99.

[13]  Mircea R. Stan.  Optimal voltages and sizing for low power [CMOS VLSI] , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[14]  Young,et al.  Dual Threshold Voltages And Substrate Bias: Keys To High Performance, Low Power, 0.1 /spl mu/m Logic Designs , 1997, 1997 Symposium on VLSI Technology.

[15]  Mircea R. Stan.  Optimal Voltages and Sizing for Low Power , 1999 .

[16]  W. Greene,et al.  0.18 um dual Vt MOSFET process and energy-delay measurement , 1996, International Electron Devices Meeting. Technical Digest.