VHDL - The Designer Environment

Part of the VHDL program is to define a support environment for the VHSIC hardware description language. This support environment is both an open-ended integration framework for what is expected to be a growing list of tools interfaced to VHDL, and a specific set of software which is being implemented in Phase B of the program. The specific software under development as part of the DoD VHDL program includes an analyzer, simulator, simplifier, reverse analyzer, and design library manager. This article summarizes the design and documentation capabilities offered the digital electronics designer by the VHDL toolset.