Improving EHW performance introducing a new decomposition strategy

This paper describes a new type of decomposition strategy for Evolvable Hardware, which tackles the problem of scalability. Several logic circuits from the MCNC benchmark have been evolved and compared with other Evolvable Hardware techniques. The results demonstrate that the proposed method improves the evolution of logic circuits in terms of time and fitness function in comparison with BIE and standard EHW.

[1]  Mehrdad Salami,et al.  Evolvable hardware at function level , 1997, Proceedings of 1997 IEEE International Conference on Evolutionary Computation (ICEC '97).

[2]  J. Miller.  An empirical study of the efficiency of learning boolean functions using a Cartesian Genetic Programming approach , 1999 .

[3]  Jim Tørresen,et al.  A Divide-and-Conquer Approach to Evolvable Hardware , 1998, ICES.

[4]  Julian Francis Miller,et al.  Scalability problems of digital circuit evolution evolvability and efficient designs , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[5]  Tatiana Kalganova,et al.  Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness , 1999, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware.

[6]  Jim Torresen,et al.  Evolving Multiplier Circuits by Training Set and Training Vector Partitioning , 2003, ICES.

[7]  Alan D. Christiansen,et al.  Towards automated evolutionary design of combinational circuits , 2000, Comput. Electr. Eng..

[8]  Jordi Madrenas,et al.  Evolvable Systems: From Biology to Hardware , 1996, Lecture Notes in Computer Science.

[9]  J. Tørresen,et al.  Increased complexity evolution applied to evolvable hardware , 1999 .

[10]  Xin Yao,et al.  Promises and challenges of evolvable hardware , 1996, IEEE Trans. Syst. Man Cybern. Part C.

[11]  David E. Goldberg,et al.  Genetic Algorithms in Search Optimization and Machine Learning , 1988 .

[12]  Tatiana Kalganova,et al.  Bidirectional incremental evolution in extrinsic evolvable hardware , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[13]  S. Yang,et al.  Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .