CMOS Storage Elements and Synchronous Logic

The number of MOSFETs in a single CMOS microprocessor chip exceeded one billion in the year 2010 and this trend has continued. Tracking the behavior of individual MOSFETs on CMOS chips in electrical testing is a daunting task. This task is simplified by following the hierarchical nature of chip architecture. Repetitive patterns in data transactions and in writing and reading data in memory arrays are implemented with a small subset of building blocks. At the next level down in the hierarchy, logic gates, storage elements, and memory cells can be independently characterized and their behaviors related to the properties of their constituent MOSFETs, interconnects, and parasitic resistances and capacitances. Circuit simulation examples to directly extract cycle time and noise margins of an SRAM cell are included.