Design Guideline of Multi-Gate MOSFETs With Substrate-Bias Control

A device design guideline of multi-gate MOSFETs with both short-channel effect immunity and a large body factor gamma is developed considering threshold-voltage control by a substrate bias. A sufficiently large gamma, at least 0.04-0.05, is essential for suppressing a subthreshold leakage current and die-to-die characteristic variation by a substrate bias. It is experimentally evaluated that gamma decreases with decreasing channel width. Channel thickness and width design space is explored by means of three-dimensional device simulations, and a thin and wide channel structure is found to be the best design for a threshold-voltage control. Thin buried oxide is advantageous for obtaining a large gamma. When the channel doping concentration is high, channel-structure design window shifts to a thinner and wider region compared to the undoped channel due to the modulation of carrier distribution in the channel. However, due to within-die random variations, highly doped design is not practical, and undoped channel design is only the solution. Required accuracy of structural parameters is also discussed. The thin and wide channel design is also advantageous in the viewpoint of the process variation

[1]  Yasuo Takahashi,et al.  Three-dimensional siloxane resist for the formation of nanopatterns with minimum linewidth fluctuations , 1998 .

[2]  T. Hiramoto,et al.  Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFET's , 2000, IEEE Electron Device Letters.

[3]  Makoto Takamiya,et al.  Separation of effects of statistical impurity number fluctuations and position distribution on Vth fluctuations in scaled MOSFETs , 2000 .

[4]  D. Delille,et al.  Highly performant double gate MOSFET realized with SON process , 2003, IEEE International Electron Devices Meeting 2003.

[5]  Toshiro Hiramoto,et al.  Short Channel Characteristics of Variable Body Factor FD SOI MOSFETs , 2004 .

[6]  Vivek De,et al.  Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[7]  Y. Yasuda,et al.  System LSI multi-vth transistors design methodology for maximizing efficiency of body-biasing control to reduce vth variation and power consumption , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[8]  T. Sekigawa,et al.  Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate , 1984 .

[9]  Chenming Hu,et al.  A folded-channel MOSFET for deep-sub-tenth micron era , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[10]  Bin Yu,et al.  FinFET scaling to 10 nm gate length , 2002, Digest. International Electron Devices Meeting,.

[11]  Andrew R. Brown,et al.  Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: a 3-D density-gradient simulation study , 2001 .

[12]  Y. Yeo,et al.  25 nm CMOS Omega FETs , 2002, Digest. International Electron Devices Meeting,.

[13]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[14]  A. Toriumi,et al.  Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's , 1994 .

[15]  D. Frank,et al.  Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[16]  Toshiro Hiramoto,et al.  Future Electron Devices and SOI Technology ?Semi-Planar SOI MOSFETs with Sufficient Body Effect? , 2003 .

[17]  T. Fujita,et al.  A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[18]  S. Takagi,et al.  On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration , 1994 .

[19]  S. Hareland,et al.  Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[20]  C.R. Cleavelin,et al.  Body effect in tri- and pi-gate SOI MOSFETs , 2004, IEEE Electron Device Letters.