Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs

Monolithic 3D (M3D) is an emerging technology that enables integration density which is orders of magnitude higher than that offered by through-silicon-vias. In this paper, we demonstrate that a modified 2D placement technique coupled with a post-placement partitioning step is sufficient to produce high-quality M3D placement solutions. We also present a commercial router-based monolithic intertier via insertion methodology that improves the routability of M3D ICs. We demonstrate that, unlike in 2D ICs, the routing supply and demand in M3D ICs are not completely independent of each other. We develop a routing demand model for M3D ICs, and use it to develop an O(N) min-overflow partitioner that enhances routability by off-loading demand from one tier to another. This technique reduces the routed wirelength and the power delay product by up to 7.44% and 4.31%, respectively. This allows a two-tier M3D IC to achieve, on average, 19.9% and 11.8% improvement in routed wirelength and power delay product over 2D, even with reduced metal layer usage.

[1]  Sung Kyu Lim,et al.  High-density integration of functional modules using monolithic 3D-IC technology , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

[2]  Ulf Schlichtmann,et al.  Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Qiang Chen,et al.  A compact physical via blockage model , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Yao-Wen Chang,et al.  Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[5]  Jason Cong,et al.  A multilevel analytical placement for 3D ICs , 2009, 2009 Asia and South Pacific Design Automation Conference.

[6]  Yao-Wen Chang,et al.  TSV-aware analytical placement for 3D IC designs , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[7]  Sung Kyu Lim,et al.  Power-performance study of block-level monolithic 3D-ICs considering inter-tier performance variations , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[8]  A. Toffoli,et al.  Advances in 3D CMOS sequential integration , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[9]  Sung Kyu Lim,et al.  Power benefit study for ultra-high density transistor-level monolithic 3D ICs , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[10]  Sung Kyu Lim,et al.  A study of Through-Silicon-Via impact on the 3D stacked IC layout , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[11]  Jin Hu,et al.  A SimPLR method for routability-driven placement , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[12]  Jason Cong,et al.  Thermal-Aware 3D IC Placement Via Transformation , 2007, 2007 Asia and South Pacific Design Automation Conference.

[13]  Chris C. N. Chu,et al.  FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Ulrich Brenner,et al.  An effective congestion driven placement framework , 2002, ISPD '02.

[15]  Giovanni De Micheli,et al.  CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[16]  Jason Cong,et al.  Routability-driven placement and white space allocation , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[17]  Kinam Kim,et al.  The revolutionary and truly 3-dimensional 25F/sup 2/ SRAM technology with the smallest S/sup 3/ ( stacked single-crystal Si) cell, 0.16um/sup 2/, and SSTFT (atacked single-crystal thin film transistor) for ultra high density SRAM , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[18]  Kinam Kim,et al.  A 500-MHz DDR High-Performance 72-Mb 3-D SRAM Fabricated With Laser-Induced Epitaxial c-Si Growth Technology for a Stand-Alone and Embedded Memory Application , 2010, IEEE Transactions on Electron Devices.

[19]  Peter Spindler,et al.  Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[20]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[21]  Jason Cong,et al.  Edge separability-based circuit clustering with application to multilevel circuit partitioning , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.