Comparison of Pinning Voltage Estimation Methods in Pinned Photodiode CMOS Image Sensors

The pinning voltage is a key design parameter of pinned photodiode CMOS image sensors which significantly affects the device performances and which is often used by manufacturers to monitor production lines and for the optimization of technological processes. This paper presents a comparative study of pinning voltage estimation methods, which are based on both electrical measurements performed on isolated test structures (or on test structures arrays) and in-pixel measurements. It is shown, with the support of simulations and experimental measurements, that not all the estimation methods provide an absolute value of the pinning voltage. Moreover, this paper demonstrates that the commonly accepted theoretical definition of the pinning voltage does not correspond to the physical parameter which is measured with the existing methods.

[1]  Donald B. Hondongwa,et al.  A Review of the Pinned Photodiode for CCD and CMOS Image Sensors , 2014, IEEE Journal of the Electron Devices Society.

[2]  James R. Janesick,et al.  Fundamental performance differences of CMOS and CCD imagers: part V , 2013, Electronic Imaging.

[3]  P. Paillet,et al.  Temperature Dependence and Dynamic Behavior of Full Well Capacity in Pinned Photodiode CMOS Image Sensors , 2015, IEEE Transactions on Electron Devices.

[4]  S. Wuu,et al.  Extraction and Estimation of Pinned Photodiode Capacitance in CMOS Image Sensors , 2014, IEEE Journal of the Electron Devices Society.

[5]  James Andrews,et al.  Fundamental performance differences between CMOS and CCD imagers: Part II , 2007, SPIE Optical Engineering + Applications.

[6]  Olivier Marcelot,et al.  Pixel Level Characterization of Pinned Photodiode and Transfer Gate Physical Parameters in CMOS Image Sensors , 2014, IEEE Journal of the Electron Devices Society.

[7]  Sangsik Park,et al.  The effect of size on photodiode pinch-off voltage for small pixel CMOS image sensors , 2009, Microelectron. J..

[8]  Francois Roy,et al.  Back Illuminated Vertically Pinned Photodiode with in Depth Charge Storage , 2011 .

[9]  R. J. Brewer.  The “barrier mode” behaviour of a junction FET at low drain currents , 1975 .

[10]  N. Blanc,et al.  Experimental Analysis of Lag Sources in Pinned Photodiodes , 2012, IEEE Electron Device Letters.

[11]  Assaf Lahav,et al.  Enhanced X-RAY CMOS sensor panel for Radio and Fluoro application using a low noise charge amplifier pixel with a Partially Pinned PD , 2011 .

[12]  Albert J. P. Theuwissen,et al.  Investigating transfer gate potential barrier by feed-forward effect measurement , 2015 .

[13]  A. S. Grove.  Physics and Technology of Semiconductor Devices , 1967 .

[14]  Shoji Kawahito,et al.  High-speed charge transfer pinned-photodiode for a CMOS time-of-flight range image sensor , 2010, Electronic Imaging.

[15]  W.M.C. Sansen,et al.  A simple model of ion-implanted JFETs valid in both the quadratic and the subthreshold regions , 1982, IEEE Journal of Solid-State Circuits.

[16]  A. J. P. Theuwissen,et al.  Analyzing the Radiation Degradation of 4-Transistor Deep Submicron Technology CMOS Image Sensors , 2012, IEEE Sensors Journal.