Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques

We present a new approach to checking assertion properties for RTL design verification. Our approach combines structural, woi-d-level automatic test pattern generation (ATPG) and modular arilhmetic constraint-solving techniques to solve the constraints imposed by the target assertion property. Our word-level ATPG and implication technique not only solves the constraints on the control logic, but also propagates the logic implications to the datapath. A novel arithmetic constraint solver based on modular number system is then employed to solve the remaining constraints in datapath. The advantages of the new method are threefold. First, the (decision-making process of the word-level ATPG is conjined to the selected control signals only. Therefore, the enumeration of enomous number of choices at the datapath signals is completely avoided. Second, our new implication translation techniques allow wond-level logic implication being performed across the boundary of datapath and control logic, and therefore, eficiently cut down the ATPG search space. Third, our arithmetic constraint solver is based on modular instead of integral number systenz. It can thus avoid the false negative effect resulting from the bit-vector value modulation. A prototype system has been built which consists of un industrial front-end HDL parser; a propertyto-constraint converter and the ATPG/arithmetic constraint-solving engine. Thc, experimental results on some public benchmurk and industrid circuits denwnstrate the ejficiency of our approach and its applicability to large industrial designs.