Open defects are extremely common in CMOS circuits. They can either be a partial or complete breaking of an input line. The complete breaking of the line is referred to as strong or full open defect. Until few years ago, a full open defect on any interconnecting line has been considered as floating. In nanometric CMOS technology, in which gate leakage currents are not negligible, full open defect lines cannot be considered to be electrically isolated. The final value of the node is independent of the initial state of the node and totally depends on the topological characteristics of the gate. Experimental evidence of the behavior of all basic gates at 90nm, 64nm and 32nm is provided, this shows a decrease in the drain current to gate leakage current ratio, in the technology scaling. The effect of full opens at the gates has also been tested by varying the PVT conditions. These variations provide a range of variation for the full open input voltage and gate leakage current. The effect of full opens on various circuits like the full adder has also been documented at various nanometric levels.
[1]
Camelia Hora,et al.
Full Open Defects in Nanometric CMOS
,
2008,
26th IEEE VLSI Test Symposium (vts 2008).
[2]
Jochen A. G. Jess,et al.
Probability analysis for CMOS floating gate faults
,
1994,
Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.
[3]
M. F.,et al.
Bibliography
,
1985,
Experimental Gerontology.
[4]
C. Hora,et al.
Impact of gate tunnelling leakage on CMOS circuits with full open defects
,
2007
.
[5]
C. Hu,et al.
Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling
,
2001
.
[6]
Simon Johnson,et al.
Residual charge on the faulty floating gate CMOS transistor
,
1994,
Proceedings., International Test Conference.